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@@ -2916,7 +2916,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
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bool disable_sclk_switching = false;
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bool disable_sclk_switching = false;
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u32 mclk, sclk;
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u32 mclk, sclk;
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u16 vddc, vddci;
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u16 vddc, vddci;
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- u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
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int i;
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int i;
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if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
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if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
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@@ -2950,29 +2949,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
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}
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}
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}
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}
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- /* limit clocks to max supported clocks based on voltage dependency tables */
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- btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
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- &max_sclk_vddc);
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- btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
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- &max_mclk_vddci);
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- btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
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- &max_mclk_vddc);
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-
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- for (i = 0; i < ps->performance_level_count; i++) {
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- if (max_sclk_vddc) {
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- if (ps->performance_levels[i].sclk > max_sclk_vddc)
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- ps->performance_levels[i].sclk = max_sclk_vddc;
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- }
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- if (max_mclk_vddci) {
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- if (ps->performance_levels[i].mclk > max_mclk_vddci)
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- ps->performance_levels[i].mclk = max_mclk_vddci;
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- }
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- if (max_mclk_vddc) {
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- if (ps->performance_levels[i].mclk > max_mclk_vddc)
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- ps->performance_levels[i].mclk = max_mclk_vddc;
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- }
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- }
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-
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/* XXX validate the min clocks required for display */
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/* XXX validate the min clocks required for display */
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if (disable_mclk_switching) {
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if (disable_mclk_switching) {
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