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@@ -861,10 +861,6 @@ static void build_audio_output(
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audio_output->crtc_info.requested_pixel_clock =
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pipe_ctx->pix_clk_params.requested_pix_clk;
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- /*
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- * TODO - Investigate why calculated pixel clk has to be
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- * requested pixel clk
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- */
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audio_output->crtc_info.calculated_pixel_clock =
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pipe_ctx->pix_clk_params.requested_pix_clk;
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@@ -1044,15 +1040,14 @@ static enum dc_status apply_single_controller_ctx_to_hw(
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stream->public.timing.display_color_depth,
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pipe_ctx->stream->signal);
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+ /* FPGA does not program backend */
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+ if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
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pipe_ctx->opp->funcs->opp_program_fmt(
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pipe_ctx->opp,
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&stream->bit_depth_params,
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&stream->clamping);
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-
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- /* FPGA does not program backend */
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- if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
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return DC_OK;
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-
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+ }
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/* TODO: move to stream encoder */
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if (pipe_ctx->stream->signal != SIGNAL_TYPE_VIRTUAL)
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if (DC_OK != bios_parser_crtc_source_select(pipe_ctx)) {
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@@ -1065,6 +1060,12 @@ static enum dc_status apply_single_controller_ctx_to_hw(
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stream->sink->link->link_enc,
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pipe_ctx->stream->signal);
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+/*vbios crtc_source_selection and encoder_setup will override fmt_C*/
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+ pipe_ctx->opp->funcs->opp_program_fmt(
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+ pipe_ctx->opp,
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+ &stream->bit_depth_params,
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+ &stream->clamping);
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+
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if (dc_is_dp_signal(pipe_ctx->stream->signal))
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pipe_ctx->stream_enc->funcs->dp_set_stream_attribute(
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pipe_ctx->stream_enc,
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