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@@ -958,7 +958,7 @@ static void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event
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/* shift the 0~7 bits to the 8~15 bits */
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/* shift the 0~7 bits to the 8~15 bits */
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reg1->config <<= 8;
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reg1->config <<= 8;
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break;
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break;
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- };
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+ }
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}
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}
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/*
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/*
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@@ -1097,7 +1097,7 @@ static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event
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hwc->config |= event->attr.config & (~0ULL << 32);
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hwc->config |= event->attr.config & (~0ULL << 32);
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reg2->config = event->attr.config2;
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reg2->config = event->attr.config2;
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break;
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break;
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- };
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+ }
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return 0;
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return 0;
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}
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}
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@@ -1135,7 +1135,7 @@ static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct per
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
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wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
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break;
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break;
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- };
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+ }
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wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
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wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
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(hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
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(hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
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