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+/*
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+ * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
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+ * Parts of this file were based on sources as follows:
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+ *
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+ * Copyright (C) 2006-2008 Intel Corporation
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+ * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
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+ * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
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+ * Copyright (C) 2011 Texas Instruments
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+ * Copyright (C) 2017 Eric Anholt
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+ *
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+ * This program is free software and is provided to you under the terms of the
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+ * GNU General Public License version 2 as published by the Free Software
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+ * Foundation, and any use by you of this program is subject to the terms of
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+ * such GNU licence.
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+ */
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+#include <linux/clk.h>
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+#include <linux/version.h>
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+#include <linux/dma-buf.h>
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+#include <linux/of_graph.h>
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+
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+#include <drm/drmP.h>
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+#include <drm/drm_panel.h>
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+#include <drm/drm_gem_cma_helper.h>
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+#include <drm/drm_fb_cma_helper.h>
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+
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+#include "tve200_drm.h"
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+
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+irqreturn_t tve200_irq(int irq, void *data)
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+{
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+ struct tve200_drm_dev_private *priv = data;
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+ u32 stat;
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+ u32 val;
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+
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+ stat = readl(priv->regs + TVE200_INT_STAT);
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+
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+ if (!stat)
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+ return IRQ_NONE;
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+
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+ /*
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+ * Vblank IRQ
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+ *
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+ * The hardware is a bit tilted: the line stays high after clearing
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+ * the vblank IRQ, firing many more interrupts. We counter this
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+ * by toggling the IRQ back and forth from firing at vblank and
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+ * firing at start of active image, which works around the problem
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+ * since those occur strictly in sequence, and we get two IRQs for each
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+ * frame, one at start of Vblank (that we make call into the CRTC) and
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+ * another one at the start of the image (that we discard).
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+ */
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+ if (stat & TVE200_INT_V_STATUS) {
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+ val = readl(priv->regs + TVE200_CTRL);
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+ /* We have an actual start of vsync */
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+ if (!(val & TVE200_VSTSTYPE_BITS)) {
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+ drm_crtc_handle_vblank(&priv->pipe.crtc);
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+ /* Toggle trigger to start of active image */
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+ val |= TVE200_VSTSTYPE_VAI;
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+ } else {
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+ /* Toggle trigger back to start of vsync */
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+ val &= ~TVE200_VSTSTYPE_BITS;
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+ }
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+ writel(val, priv->regs + TVE200_CTRL);
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+ } else
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+ dev_err(priv->drm->dev, "stray IRQ %08x\n", stat);
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+
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+ /* Clear the interrupt once done */
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+ writel(stat, priv->regs + TVE200_INT_CLR);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static int tve200_display_check(struct drm_simple_display_pipe *pipe,
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+ struct drm_plane_state *pstate,
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+ struct drm_crtc_state *cstate)
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+{
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+ const struct drm_display_mode *mode = &cstate->mode;
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+ struct drm_framebuffer *old_fb = pipe->plane.state->fb;
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+ struct drm_framebuffer *fb = pstate->fb;
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+
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+ /*
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+ * We support these specific resolutions and nothing else.
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+ */
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+ if (!(mode->hdisplay == 352 && mode->vdisplay == 240) && /* SIF(525) */
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+ !(mode->hdisplay == 352 && mode->vdisplay == 288) && /* CIF(625) */
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+ !(mode->hdisplay == 640 && mode->vdisplay == 480) && /* VGA */
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+ !(mode->hdisplay == 720 && mode->vdisplay == 480) && /* D1 */
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+ !(mode->hdisplay == 720 && mode->vdisplay == 576)) { /* D1 */
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+ DRM_DEBUG_KMS("unsupported display mode (%u x %u)\n",
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+ mode->hdisplay, mode->vdisplay);
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+ return -EINVAL;
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+ }
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+
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+ if (fb) {
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+ u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
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+
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+ /* FB base address must be dword aligned. */
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+ if (offset & 3) {
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+ DRM_DEBUG_KMS("FB not 32-bit aligned\n");
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+ return -EINVAL;
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+ }
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+
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+ /*
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+ * There's no pitch register, the mode's hdisplay
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+ * controls this.
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+ */
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+ if (fb->pitches[0] != mode->hdisplay * fb->format->cpp[0]) {
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+ DRM_DEBUG_KMS("can't handle pitches\n");
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+ return -EINVAL;
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+ }
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+
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+ /*
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+ * We can't change the FB format in a flicker-free
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+ * manner (and only update it during CRTC enable).
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+ */
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+ if (old_fb && old_fb->format != fb->format)
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+ cstate->mode_changed = true;
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+ }
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+
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+ return 0;
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+}
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+
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+static void tve200_display_enable(struct drm_simple_display_pipe *pipe,
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+ struct drm_crtc_state *cstate)
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+{
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+ struct drm_crtc *crtc = &pipe->crtc;
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+ struct drm_plane *plane = &pipe->plane;
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+ struct drm_device *drm = crtc->dev;
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+ struct tve200_drm_dev_private *priv = drm->dev_private;
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+ const struct drm_display_mode *mode = &cstate->mode;
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+ struct drm_framebuffer *fb = plane->state->fb;
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+ struct drm_connector *connector = &priv->connector.connector;
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+ u32 format = fb->format->format;
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+ u32 ctrl1 = 0;
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+
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+ clk_prepare_enable(priv->clk);
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+
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+ /* Function 1 */
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+ ctrl1 |= TVE200_CTRL_CSMODE;
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+ /* Interlace mode for CCIR656: parameterize? */
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+ ctrl1 |= TVE200_CTRL_NONINTERLACE;
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+ /* 32 words per burst */
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+ ctrl1 |= TVE200_CTRL_BURST_32_WORDS;
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+ /* 16 retries */
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+ ctrl1 |= TVE200_CTRL_RETRYCNT_16;
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+ /* NTSC mode: parametrize? */
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+ ctrl1 |= TVE200_CTRL_NTSC;
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+
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+ /* Vsync IRQ at start of Vsync at first */
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+ ctrl1 |= TVE200_VSTSTYPE_VSYNC;
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+
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+ if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
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+ ctrl1 |= TVE200_CTRL_TVCLKP;
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+
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+ if ((mode->hdisplay == 352 && mode->vdisplay == 240) || /* SIF(525) */
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+ (mode->hdisplay == 352 && mode->vdisplay == 288)) { /* CIF(625) */
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+ ctrl1 |= TVE200_CTRL_IPRESOL_CIF;
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+ dev_info(drm->dev, "CIF mode\n");
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+ } else if (mode->hdisplay == 640 && mode->vdisplay == 480) {
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+ ctrl1 |= TVE200_CTRL_IPRESOL_VGA;
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+ dev_info(drm->dev, "VGA mode\n");
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+ } else if ((mode->hdisplay == 720 && mode->vdisplay == 480) ||
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+ (mode->hdisplay == 720 && mode->vdisplay == 576)) {
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+ ctrl1 |= TVE200_CTRL_IPRESOL_D1;
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+ dev_info(drm->dev, "D1 mode\n");
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+ }
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+
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+ if (format & DRM_FORMAT_BIG_ENDIAN) {
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+ ctrl1 |= TVE200_CTRL_BBBP;
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+ format &= ~DRM_FORMAT_BIG_ENDIAN;
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+ }
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+
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+ switch (format) {
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+ case DRM_FORMAT_XRGB8888:
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+ ctrl1 |= TVE200_IPDMOD_RGB888;
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+ break;
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+ case DRM_FORMAT_RGB565:
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+ ctrl1 |= TVE200_IPDMOD_RGB565;
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+ break;
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+ case DRM_FORMAT_XRGB1555:
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+ ctrl1 |= TVE200_IPDMOD_RGB555;
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+ break;
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+ case DRM_FORMAT_XBGR8888:
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+ ctrl1 |= TVE200_IPDMOD_RGB888 | TVE200_BGR;
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+ break;
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+ case DRM_FORMAT_BGR565:
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+ ctrl1 |= TVE200_IPDMOD_RGB565 | TVE200_BGR;
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+ break;
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+ case DRM_FORMAT_XBGR1555:
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+ ctrl1 |= TVE200_IPDMOD_RGB555 | TVE200_BGR;
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+ break;
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+ case DRM_FORMAT_YUYV:
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+ ctrl1 |= TVE200_IPDMOD_YUV422;
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+ ctrl1 |= TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0;
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+ break;
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+ case DRM_FORMAT_YVYU:
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+ ctrl1 |= TVE200_IPDMOD_YUV422;
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+ ctrl1 |= TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0;
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+ break;
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+ case DRM_FORMAT_UYVY:
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+ ctrl1 |= TVE200_IPDMOD_YUV422;
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+ ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0;
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+ break;
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+ case DRM_FORMAT_VYUY:
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+ ctrl1 |= TVE200_IPDMOD_YUV422;
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+ ctrl1 |= TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0;
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+ break;
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+ case DRM_FORMAT_YUV420:
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+ ctrl1 |= TVE200_CTRL_YUV420;
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+ ctrl1 |= TVE200_IPDMOD_YUV420;
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+ break;
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+ default:
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+ dev_err(drm->dev, "Unknown FB format 0x%08x\n",
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+ fb->format->format);
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+ break;
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+ }
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+
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+ ctrl1 |= TVE200_TVEEN;
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+
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+ drm_panel_prepare(priv->connector.panel);
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+
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+ /* Turn it on */
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+ writel(ctrl1, priv->regs + TVE200_CTRL);
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+
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+ drm_panel_enable(priv->connector.panel);
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+
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+ drm_crtc_vblank_on(crtc);
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+}
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+
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+void tve200_display_disable(struct drm_simple_display_pipe *pipe)
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+{
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+ struct drm_crtc *crtc = &pipe->crtc;
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+ struct drm_device *drm = crtc->dev;
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+ struct tve200_drm_dev_private *priv = drm->dev_private;
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+
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+ drm_crtc_vblank_off(crtc);
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+
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+ drm_panel_disable(priv->connector.panel);
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+
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+ /* Disable and Power Down */
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+ writel(0, priv->regs + TVE200_CTRL);
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+
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+ drm_panel_unprepare(priv->connector.panel);
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+
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+ clk_disable_unprepare(priv->clk);
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+}
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+
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+static void tve200_display_update(struct drm_simple_display_pipe *pipe,
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+ struct drm_plane_state *old_pstate)
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+{
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+ struct drm_crtc *crtc = &pipe->crtc;
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+ struct drm_device *drm = crtc->dev;
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+ struct tve200_drm_dev_private *priv = drm->dev_private;
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+ struct drm_pending_vblank_event *event = crtc->state->event;
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+ struct drm_plane *plane = &pipe->plane;
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+ struct drm_plane_state *pstate = plane->state;
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+ struct drm_framebuffer *fb = pstate->fb;
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+
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+ if (fb) {
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+ /* For RGB, the Y component is used as base address */
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+ writel(drm_fb_cma_get_gem_addr(fb, pstate, 0),
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+ priv->regs + TVE200_Y_FRAME_BASE_ADDR);
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+
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+ /* For three plane YUV we need two more addresses */
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+ if (fb->format->format == DRM_FORMAT_YUV420) {
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+ writel(drm_fb_cma_get_gem_addr(fb, pstate, 1),
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+ priv->regs + TVE200_U_FRAME_BASE_ADDR);
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+ writel(drm_fb_cma_get_gem_addr(fb, pstate, 2),
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+ priv->regs + TVE200_V_FRAME_BASE_ADDR);
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+ }
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+ }
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+
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+ if (event) {
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+ crtc->state->event = NULL;
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+
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+ spin_lock_irq(&crtc->dev->event_lock);
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+ if (crtc->state->active && drm_crtc_vblank_get(crtc) == 0)
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+ drm_crtc_arm_vblank_event(crtc, event);
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+ else
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+ drm_crtc_send_vblank_event(crtc, event);
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+ spin_unlock_irq(&crtc->dev->event_lock);
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+ }
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+}
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+
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+int tve200_enable_vblank(struct drm_device *drm, unsigned int crtc)
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+{
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+ struct tve200_drm_dev_private *priv = drm->dev_private;
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+
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+ writel(TVE200_INT_V_STATUS, priv->regs + TVE200_INT_EN);
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+ return 0;
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+}
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+
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+void tve200_disable_vblank(struct drm_device *drm, unsigned int crtc)
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+{
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+ struct tve200_drm_dev_private *priv = drm->dev_private;
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+
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+ writel(0, priv->regs + TVE200_INT_EN);
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+}
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+
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+static int tve200_display_prepare_fb(struct drm_simple_display_pipe *pipe,
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+ struct drm_plane_state *plane_state)
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+{
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+ return drm_fb_cma_prepare_fb(&pipe->plane, plane_state);
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+}
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+
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+const struct drm_simple_display_pipe_funcs tve200_display_funcs = {
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+ .check = tve200_display_check,
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+ .enable = tve200_display_enable,
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+ .disable = tve200_display_disable,
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+ .update = tve200_display_update,
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+ .prepare_fb = tve200_display_prepare_fb,
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+};
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+
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+int tve200_display_init(struct drm_device *drm)
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+{
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+ struct tve200_drm_dev_private *priv = drm->dev_private;
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+ int ret;
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+ static const u32 formats[] = {
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+ DRM_FORMAT_XRGB8888,
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+ DRM_FORMAT_XBGR8888,
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+ DRM_FORMAT_RGB565,
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+ DRM_FORMAT_BGR565,
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+ DRM_FORMAT_XRGB1555,
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+ DRM_FORMAT_XBGR1555,
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+ /*
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+ * The controller actually supports any YCbCr ordering,
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+ * for packed YCbCr. This just lists the orderings that
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+ * DRM supports.
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+ */
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+ DRM_FORMAT_YUYV,
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+ DRM_FORMAT_YVYU,
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+ DRM_FORMAT_UYVY,
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+ DRM_FORMAT_VYUY,
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+ /* This uses three planes */
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+ DRM_FORMAT_YUV420,
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+ };
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+
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+ ret = drm_simple_display_pipe_init(drm, &priv->pipe,
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+ &tve200_display_funcs,
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+ formats, ARRAY_SIZE(formats),
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+ &priv->connector.connector);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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