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@@ -56,6 +56,12 @@ Required properties:
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On (H)SCI(F) and some SCIFA, an additional clock may be specified:
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On (H)SCI(F) and some SCIFA, an additional clock may be specified:
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- "hsck" for the optional external clock input (on HSCIF),
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- "hsck" for the optional external clock input (on HSCIF),
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- "sck" for the optional external clock input (on other variants).
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- "sck" for the optional external clock input (on other variants).
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+ On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
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+ (some SCIF and HSCIF), additional clocks may be specified:
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+ - "brg_int" for the optional internal clock source for the frequency
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+ divider (typically the (AXI or SHwy) bus clock),
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+ - "scif_clk" for the optional external clock source for the frequency
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+ divider (SCIF_CLK).
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Note: Each enabled SCIx UART should have an alias correctly numbered in the
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Note: Each enabled SCIx UART should have an alias correctly numbered in the
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"aliases" node.
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"aliases" node.
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