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@@ -1224,11 +1224,32 @@ static int imx_startup(struct uart_port *port)
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temp |= (UCR2_RXEN | UCR2_TXEN);
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if (!sport->have_rtscts)
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temp |= UCR2_IRTS;
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+ /*
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+ * make sure the edge sensitive RTS-irq is disabled,
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+ * we're using RTSD instead.
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+ */
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+ if (!is_imx1_uart(sport))
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+ temp &= ~UCR2_RTSEN;
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writel(temp, sport->port.membase + UCR2);
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if (!is_imx1_uart(sport)) {
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temp = readl(sport->port.membase + UCR3);
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- temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
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+
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+ /*
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+ * The effect of RI and DCD differs depending on the UFCR_DCEDTE
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+ * bit. In DCE mode they control the outputs, in DTE mode they
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+ * enable the respective irqs. At least the DCD irq cannot be
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+ * cleared on i.MX25 at least, so it's not usable and must be
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+ * disabled. I don't have test hardware to check if RI has the
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+ * same problem but I consider this likely so it's disabled for
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+ * now, too.
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+ */
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+ temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP |
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+ UCR3_RI | UCR3_DCD;
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+
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+ if (sport->dte_mode)
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+ temp &= ~(UCR3_RI | UCR3_DCD);
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+
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writel(temp, sport->port.membase + UCR3);
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}
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