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@@ -82,6 +82,15 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
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return -EINVAL;
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return -EINVAL;
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}
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}
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break;
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break;
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+ case AMDGPU_HW_IP_UVD_ENC:
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+ if (ring < adev->uvd.num_enc_rings){
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+ *out_ring = &adev->uvd.ring_enc[ring];
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+ } else {
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+ DRM_ERROR("only %d UVD ENC rings are supported\n",
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+ adev->uvd.num_enc_rings);
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+ return -EINVAL;
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+ }
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+ break;
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}
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}
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if (!(*out_ring && (*out_ring)->adev)) {
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if (!(*out_ring && (*out_ring)->adev)) {
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