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@@ -3418,6 +3418,10 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg,
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/* configure the core to support LPM */
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/* configure the core to support LPM */
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dwc2_gadget_init_lpm(hsotg);
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dwc2_gadget_init_lpm(hsotg);
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+ /* program GREFCLK register if needed */
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+ if (using_desc_dma(hsotg) && hsotg->params.service_interval)
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+ dwc2_gadget_program_ref_clk(hsotg);
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+
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/* must be at-least 3ms to allow bus to see disconnect */
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/* must be at-least 3ms to allow bus to see disconnect */
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mdelay(3);
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mdelay(3);
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@@ -5001,6 +5005,25 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg)
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dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
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dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG));
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}
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}
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+/**
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+ * dwc2_gadget_program_ref_clk - Program GREFCLK register in device mode
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+ *
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+ * @hsotg: Programming view of DWC_otg controller
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+ *
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+ */
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+void dwc2_gadget_program_ref_clk(struct dwc2_hsotg *hsotg)
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+{
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+ u32 val = 0;
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+
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+ val |= GREFCLK_REF_CLK_MODE;
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+ val |= hsotg->params.ref_clk_per << GREFCLK_REFCLKPER_SHIFT;
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+ val |= hsotg->params.sof_cnt_wkup_alert <<
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+ GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT;
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+
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+ dwc2_writel(hsotg, val, GREFCLK);
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+ dev_dbg(hsotg->dev, "GREFCLK=0x%08x\n", dwc2_readl(hsotg, GREFCLK));
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+}
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+
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/**
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/**
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* dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
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* dwc2_gadget_enter_hibernation() - Put controller in Hibernation.
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*
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*
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