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@@ -34,6 +34,13 @@
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#define KXCJK1013_DRV_NAME "kxcjk1013"
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#define KXCJK1013_DRV_NAME "kxcjk1013"
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#define KXCJK1013_IRQ_NAME "kxcjk1013_event"
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#define KXCJK1013_IRQ_NAME "kxcjk1013_event"
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+#define KXTF9_REG_HP_XOUT_L 0x00
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+#define KXTF9_REG_HP_XOUT_H 0x01
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+#define KXTF9_REG_HP_YOUT_L 0x02
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+#define KXTF9_REG_HP_YOUT_H 0x03
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+#define KXTF9_REG_HP_ZOUT_L 0x04
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+#define KXTF9_REG_HP_ZOUT_H 0x05
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+
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#define KXCJK1013_REG_XOUT_L 0x06
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#define KXCJK1013_REG_XOUT_L 0x06
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/*
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/*
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* From low byte X axis register, all the other addresses of Y and Z can be
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* From low byte X axis register, all the other addresses of Y and Z can be
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@@ -48,17 +55,33 @@
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#define KXCJK1013_REG_DCST_RESP 0x0C
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#define KXCJK1013_REG_DCST_RESP 0x0C
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#define KXCJK1013_REG_WHO_AM_I 0x0F
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#define KXCJK1013_REG_WHO_AM_I 0x0F
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-#define KXCJK1013_REG_INT_SRC1 0x16
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+#define KXTF9_REG_TILT_POS_CUR 0x10
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+#define KXTF9_REG_TILT_POS_PREV 0x11
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+#define KXTF9_REG_INT_SRC1 0x15
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+#define KXCJK1013_REG_INT_SRC1 0x16 /* compatible, but called INT_SRC2 in KXTF9 ds */
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#define KXCJK1013_REG_INT_SRC2 0x17
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#define KXCJK1013_REG_INT_SRC2 0x17
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#define KXCJK1013_REG_STATUS_REG 0x18
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#define KXCJK1013_REG_STATUS_REG 0x18
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#define KXCJK1013_REG_INT_REL 0x1A
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#define KXCJK1013_REG_INT_REL 0x1A
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#define KXCJK1013_REG_CTRL1 0x1B
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#define KXCJK1013_REG_CTRL1 0x1B
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-#define KXCJK1013_REG_CTRL2 0x1D
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+#define KXTF9_REG_CTRL2 0x1C
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+#define KXCJK1013_REG_CTRL2 0x1D /* mostly compatible, CTRL_REG3 in KTXF9 ds */
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#define KXCJK1013_REG_INT_CTRL1 0x1E
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#define KXCJK1013_REG_INT_CTRL1 0x1E
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#define KXCJK1013_REG_INT_CTRL2 0x1F
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#define KXCJK1013_REG_INT_CTRL2 0x1F
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+#define KXTF9_REG_INT_CTRL3 0x20
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#define KXCJK1013_REG_DATA_CTRL 0x21
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#define KXCJK1013_REG_DATA_CTRL 0x21
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+#define KXTF9_REG_TILT_TIMER 0x28
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#define KXCJK1013_REG_WAKE_TIMER 0x29
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#define KXCJK1013_REG_WAKE_TIMER 0x29
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+#define KXTF9_REG_TDT_TIMER 0x2B
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+#define KXTF9_REG_TDT_THRESH_H 0x2C
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+#define KXTF9_REG_TDT_THRESH_L 0x2D
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+#define KXTF9_REG_TDT_TAP_TIMER 0x2E
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+#define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
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+#define KXTF9_REG_TDT_LATENCY_TIMER 0x30
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+#define KXTF9_REG_TDT_WINDOW_TIMER 0x31
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#define KXCJK1013_REG_SELF_TEST 0x3A
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#define KXCJK1013_REG_SELF_TEST 0x3A
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+#define KXTF9_REG_WAKE_THRESH 0x5A
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+#define KXTF9_REG_TILT_ANGLE 0x5C
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+#define KXTF9_REG_HYST_SET 0x5F
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#define KXCJK1013_REG_WAKE_THRES 0x6A
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#define KXCJK1013_REG_WAKE_THRES 0x6A
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#define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
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#define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
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@@ -68,18 +91,32 @@
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#define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
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#define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
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#define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
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#define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
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+#define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
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#define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
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#define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
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#define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
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#define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
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#define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
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#define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
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+#define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
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+#define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
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+#define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
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+#define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
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+#define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
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+#define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
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+
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#define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
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#define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
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#define KXCJK1013_MAX_STARTUP_TIME_US 100000
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#define KXCJK1013_MAX_STARTUP_TIME_US 100000
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#define KXCJK1013_SLEEP_DELAY_MS 2000
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#define KXCJK1013_SLEEP_DELAY_MS 2000
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+#define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
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#define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
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#define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
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+#define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
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+#define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
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+#define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
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+#define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
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#define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
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#define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
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+/* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
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#define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
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#define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
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#define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
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#define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
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#define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
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#define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
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@@ -93,6 +130,7 @@ enum kx_chipset {
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KXCJK1013,
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KXCJK1013,
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KXCJ91008,
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KXCJ91008,
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KXTJ21009,
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KXTJ21009,
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+ KXTF9,
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KX_MAX_CHIPS /* this must be last */
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KX_MAX_CHIPS /* this must be last */
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};
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};
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@@ -158,6 +196,18 @@ static const struct kx_odr_map samp_freq_table[] = {
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static const char *const kxcjk1013_samp_freq_avail =
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static const char *const kxcjk1013_samp_freq_avail =
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"0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
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"0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
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+static const struct kx_odr_map kxtf9_samp_freq_table[] = {
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+ { 25, 0, 0x01, 0x00 },
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+ { 50, 0, 0x02, 0x01 },
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+ { 100, 0, 0x03, 0x01 },
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+ { 200, 0, 0x04, 0x01 },
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+ { 400, 0, 0x05, 0x01 },
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+ { 800, 0, 0x06, 0x01 },
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+};
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+
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+static const char *const kxtf9_samp_freq_avail =
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+ "25 50 100 200 400 800";
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+
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/* Refer to section 4 of the specification */
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/* Refer to section 4 of the specification */
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static const struct {
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static const struct {
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int odr_bits;
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int odr_bits;
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@@ -208,6 +258,15 @@ static const struct {
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{0x06, 3000},
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{0x06, 3000},
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{0x07, 2000},
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{0x07, 2000},
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},
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},
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+ /* KXTF9 */
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+ {
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+ {0x01, 81000},
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+ {0x02, 41000},
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+ {0x03, 21000},
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+ {0x04, 11000},
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+ {0x05, 5100},
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+ {0x06, 2700},
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+ },
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};
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};
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static const struct {
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static const struct {
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@@ -404,7 +463,7 @@ static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
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static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
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static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
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{
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{
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- int ret;
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+ int waketh_reg, ret;
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ret = i2c_smbus_write_byte_data(data->client,
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ret = i2c_smbus_write_byte_data(data->client,
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KXCJK1013_REG_WAKE_TIMER,
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KXCJK1013_REG_WAKE_TIMER,
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@@ -415,8 +474,9 @@ static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
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return ret;
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return ret;
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}
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}
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- ret = i2c_smbus_write_byte_data(data->client,
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- KXCJK1013_REG_WAKE_THRES,
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+ waketh_reg = data->chipset == KXTF9 ?
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+ KXTF9_REG_WAKE_THRESH : KXCJK1013_REG_WAKE_THRES;
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+ ret = i2c_smbus_write_byte_data(data->client, waketh_reg,
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data->wake_thres);
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data->wake_thres);
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if (ret < 0) {
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if (ret < 0) {
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dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
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dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
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@@ -590,9 +650,14 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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- odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
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- ARRAY_SIZE(samp_freq_table),
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- val, val2);
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+ if (data->chipset == KXTF9)
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+ odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
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+ ARRAY_SIZE(kxtf9_samp_freq_table),
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+ val, val2);
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+ else
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+ odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
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+ ARRAY_SIZE(samp_freq_table),
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+ val, val2);
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if (IS_ERR(odr_setting))
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if (IS_ERR(odr_setting))
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return PTR_ERR(odr_setting);
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return PTR_ERR(odr_setting);
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@@ -629,9 +694,14 @@ static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
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static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
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static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
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{
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{
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- return kxcjk1013_convert_odr_value(samp_freq_table,
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- ARRAY_SIZE(samp_freq_table),
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- data->odr_bits, val, val2);
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+ if (data->chipset == KXTF9)
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+ return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
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+ ARRAY_SIZE(kxtf9_samp_freq_table),
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+ data->odr_bits, val, val2);
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+ else
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+ return kxcjk1013_convert_odr_value(samp_freq_table,
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+ ARRAY_SIZE(samp_freq_table),
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+ data->odr_bits, val, val2);
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}
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}
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static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
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static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
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@@ -886,7 +956,16 @@ static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
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struct device_attribute *attr,
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struct device_attribute *attr,
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char *buf)
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char *buf)
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{
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{
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- return sprintf(buf, "%s\n", kxcjk1013_samp_freq_avail);
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+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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+ struct kxcjk1013_data *data = iio_priv(indio_dev);
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+ const char *str;
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+
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+ if (data->chipset == KXTF9)
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+ str = kxtf9_samp_freq_avail;
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+ else
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+ str = kxcjk1013_samp_freq_avail;
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+
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+ return sprintf(buf, "%s\n", str);
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}
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}
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static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
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static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
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@@ -1119,7 +1198,16 @@ static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
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}
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}
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if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
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if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
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- kxcjk1013_report_motion_event(indio_dev);
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+ if (data->chipset == KXTF9)
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+ iio_push_event(indio_dev,
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+ IIO_MOD_EVENT_CODE(IIO_ACCEL,
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+ 0,
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+ IIO_MOD_X_AND_Y_AND_Z,
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+ IIO_EV_TYPE_THRESH,
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+ IIO_EV_DIR_RISING),
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+ data->timestamp);
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+ else
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+ kxcjk1013_report_motion_event(indio_dev);
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}
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}
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ack_intr:
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ack_intr:
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@@ -1412,6 +1500,7 @@ static const struct i2c_device_id kxcjk1013_id[] = {
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{"kxcjk1013", KXCJK1013},
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{"kxcjk1013", KXCJK1013},
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{"kxcj91008", KXCJ91008},
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{"kxcj91008", KXCJ91008},
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{"kxtj21009", KXTJ21009},
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{"kxtj21009", KXTJ21009},
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+ {"kxtf9", KXTF9},
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{"SMO8500", KXCJ91008},
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{"SMO8500", KXCJ91008},
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{}
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{}
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};
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};
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