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@@ -1171,6 +1171,16 @@ static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
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UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
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UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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+ if (ret_code) {
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+ int tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
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+ /* wait for read ptr to be equal to write ptr */
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+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code);
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+
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+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
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+ UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
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+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
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+ }
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+
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/* disable dynamic power gating mode */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
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~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
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