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@@ -1121,6 +1121,71 @@ static struct omap_hwmod omap54xx_mmc5_hwmod = {
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},
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},
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};
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};
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+/*
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+ * 'mmu' class
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+ * The memory management unit performs virtual to physical address translation
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+ * for its requestors.
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+ */
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+
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+static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
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+ .rev_offs = 0x0000,
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+ .sysc_offs = 0x0010,
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+ .syss_offs = 0x0014,
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+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
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+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
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+ SYSS_HAS_RESET_STATUS),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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+ .sysc_fields = &omap_hwmod_sysc_type1,
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+};
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+
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+static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
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+ .name = "mmu",
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+ .sysc = &omap54xx_mmu_sysc,
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+};
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+
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+static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
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+ { .name = "mmu_cache", .rst_shift = 1 },
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+};
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+
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+static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
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+ .name = "mmu_dsp",
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+ .class = &omap54xx_mmu_hwmod_class,
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+ .clkdm_name = "dsp_clkdm",
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+ .rst_lines = omap54xx_mmu_dsp_resets,
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+ .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
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+ .main_clk = "dpll_iva_h11x2_ck",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
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+ .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
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+ .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_HWCTRL,
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+ },
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+ },
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+};
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+
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+/* mmu ipu */
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+static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
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+ { .name = "mmu_cache", .rst_shift = 2 },
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+};
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+
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+static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
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+ .name = "mmu_ipu",
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+ .class = &omap54xx_mmu_hwmod_class,
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+ .clkdm_name = "ipu_clkdm",
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+ .rst_lines = omap54xx_mmu_ipu_resets,
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+ .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
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+ .main_clk = "dpll_core_h22x2_ck",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
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+ .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
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+ .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_HWCTRL,
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+ },
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+ },
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+};
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+
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/*
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/*
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* 'mpu' class
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* 'mpu' class
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* mpu sub-system
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* mpu sub-system
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@@ -1763,6 +1828,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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};
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+/* l4_cfg -> mmu_dsp */
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+static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
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+ .master = &omap54xx_l4_cfg_hwmod,
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+ .slave = &omap54xx_mmu_dsp_hwmod,
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+ .clk = "l4_root_clk_div",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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/* mpu -> l3_main_1 */
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/* mpu -> l3_main_1 */
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static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
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static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
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.master = &omap54xx_mpu_hwmod,
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.master = &omap54xx_mpu_hwmod,
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@@ -1787,6 +1860,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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};
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+/* l3_main_2 -> mmu_ipu */
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+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
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+ .master = &omap54xx_l3_main_2_hwmod,
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+ .slave = &omap54xx_mmu_ipu_hwmod,
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+ .clk = "l3_iclk_div",
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+ .user = OCP_USER_MPU | OCP_USER_SDMA,
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+};
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+
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/* l3_main_1 -> l3_main_3 */
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/* l3_main_1 -> l3_main_3 */
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
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static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
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.master = &omap54xx_l3_main_1_hwmod,
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.master = &omap54xx_l3_main_1_hwmod,
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@@ -2345,6 +2426,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
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&omap54xx_l4_wkup__counter_32k,
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&omap54xx_l4_wkup__counter_32k,
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&omap54xx_l4_cfg__dma_system,
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&omap54xx_l4_cfg__dma_system,
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&omap54xx_l4_abe__dmic,
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&omap54xx_l4_abe__dmic,
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+ &omap54xx_l4_cfg__mmu_dsp,
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&omap54xx_mpu__emif1,
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&omap54xx_mpu__emif1,
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&omap54xx_mpu__emif2,
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&omap54xx_mpu__emif2,
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&omap54xx_l4_wkup__gpio1,
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&omap54xx_l4_wkup__gpio1,
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@@ -2360,6 +2442,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
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&omap54xx_l4_per__i2c3,
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&omap54xx_l4_per__i2c3,
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&omap54xx_l4_per__i2c4,
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&omap54xx_l4_per__i2c4,
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&omap54xx_l4_per__i2c5,
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&omap54xx_l4_per__i2c5,
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+ &omap54xx_l3_main_2__mmu_ipu,
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&omap54xx_l4_wkup__kbd,
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&omap54xx_l4_wkup__kbd,
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&omap54xx_l4_cfg__mailbox,
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&omap54xx_l4_cfg__mailbox,
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&omap54xx_l4_abe__mcbsp1,
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&omap54xx_l4_abe__mcbsp1,
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