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@@ -1194,7 +1194,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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struct intel_shared_dpll *pll;
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uint32_t ctrl1, cfgcr1, cfgcr2;
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int clock = crtc_state->port_clock;
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- uint32_t vco = 8100;
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/*
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* See comment in intel_dpll_hw_state to understand why we always use 0
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@@ -1239,15 +1238,12 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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break;
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case 108000:
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ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
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- vco = 8640;
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break;
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case 216000:
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ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
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- vco = 8640;
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break;
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}
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- to_intel_atomic_state(crtc_state->base.state)->cdclk_pll_vco = vco;
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cfgcr1 = cfgcr2 = 0;
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} else {
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return NULL;
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