|
@@ -269,9 +269,6 @@
|
|
|
#define STRTAB_STE_1_SHCFG_INCOMING 1UL
|
|
|
#define STRTAB_STE_1_SHCFG_SHIFT 44
|
|
|
|
|
|
-#define STRTAB_STE_1_PRIVCFG_UNPRIV 2UL
|
|
|
-#define STRTAB_STE_1_PRIVCFG_SHIFT 48
|
|
|
-
|
|
|
#define STRTAB_STE_2_S2VMID_SHIFT 0
|
|
|
#define STRTAB_STE_2_S2VMID_MASK 0xffffUL
|
|
|
#define STRTAB_STE_2_VTCR_SHIFT 32
|
|
@@ -1073,9 +1070,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
|
|
|
#ifdef CONFIG_PCI_ATS
|
|
|
STRTAB_STE_1_EATS_TRANS << STRTAB_STE_1_EATS_SHIFT |
|
|
|
#endif
|
|
|
- STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT |
|
|
|
- STRTAB_STE_1_PRIVCFG_UNPRIV <<
|
|
|
- STRTAB_STE_1_PRIVCFG_SHIFT);
|
|
|
+ STRTAB_STE_1_STRW_NSEL1 << STRTAB_STE_1_STRW_SHIFT);
|
|
|
|
|
|
if (smmu->features & ARM_SMMU_FEAT_STALLS)
|
|
|
dst[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD);
|