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@@ -669,6 +669,27 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev)
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return 0;
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}
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+static void
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+sdma_v4_1_update_power_gating(struct amdgpu_device *adev, bool enable)
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+{
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+ uint32_t def, data;
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+
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+ if (enable && (adev->pg_flags & AMD_PG_SUPPORT_SDMA)) {
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+ /* disable idle interrupt */
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+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
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+ data |= SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
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+
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+ if (data != def)
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+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
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+ } else {
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+ /* disable idle interrupt */
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+ def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL));
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+ data &= ~SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK;
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+ if (data != def)
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+ WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CNTL), data);
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+ }
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+}
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+
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static void sdma_v4_1_init_power_gating(struct amdgpu_device *adev)
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{
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uint32_t def, data;
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@@ -704,6 +725,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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sdma_v4_1_init_power_gating(adev);
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+ sdma_v4_1_update_power_gating(adev, true);
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break;
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default:
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break;
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@@ -1502,6 +1524,17 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
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static int sdma_v4_0_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+
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+ switch (adev->asic_type) {
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+ case CHIP_RAVEN:
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+ sdma_v4_1_update_power_gating(adev,
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+ state == AMD_PG_STATE_GATE ? true : false);
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+ break;
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+ default:
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+ break;
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+ }
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+
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return 0;
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}
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