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@@ -37,6 +37,7 @@
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#include <asm/pci-bridge.h>
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#include <asm/ppc-pci.h>
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#include <asm/machdep.h>
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+#include <asm/mpc85xx.h>
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#include <asm/disassemble.h>
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#include <asm/ppc-opcode.h>
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#include <sysdev/fsl_soc.h>
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@@ -527,6 +528,8 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
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u8 hdr_type, progif;
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struct device_node *dev;
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struct ccsr_pci __iomem *pci;
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+ u16 temp;
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+ u32 svr = mfspr(SPRN_SVR);
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dev = pdev->dev.of_node;
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@@ -596,6 +599,27 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
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PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
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if (fsl_pcie_check_link(hose))
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hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
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+ } else {
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+ /*
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+ * Set PBFR(PCI Bus Function Register)[10] = 1 to
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+ * disable the combining of crossing cacheline
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+ * boundary requests into one burst transaction.
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+ * PCI-X operation is not affected.
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+ * Fix erratum PCI 5 on MPC8548
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+ */
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+#define PCI_BUS_FUNCTION 0x44
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+#define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */
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+ if (((SVR_SOC_VER(svr) == SVR_8543) ||
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+ (SVR_SOC_VER(svr) == SVR_8545) ||
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+ (SVR_SOC_VER(svr) == SVR_8547) ||
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+ (SVR_SOC_VER(svr) == SVR_8548)) &&
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+ !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
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+ early_read_config_word(hose, 0, 0,
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+ PCI_BUS_FUNCTION, &temp);
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+ temp |= PCI_BUS_FUNCTION_MDS;
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+ early_write_config_word(hose, 0, 0,
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+ PCI_BUS_FUNCTION, temp);
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+ }
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}
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printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
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