|
@@ -16,6 +16,50 @@
|
|
|
PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_MASK_MCHECK | \
|
|
|
PSW_MASK_PSTATE | PSW_ASC_PRIMARY)
|
|
|
|
|
|
+struct psw_bits {
|
|
|
+ unsigned long long : 1;
|
|
|
+ unsigned long long r : 1; /* PER-Mask */
|
|
|
+ unsigned long long : 3;
|
|
|
+ unsigned long long t : 1; /* DAT Mode */
|
|
|
+ unsigned long long i : 1; /* Input/Output Mask */
|
|
|
+ unsigned long long e : 1; /* External Mask */
|
|
|
+ unsigned long long key : 4; /* PSW Key */
|
|
|
+ unsigned long long : 1;
|
|
|
+ unsigned long long m : 1; /* Machine-Check Mask */
|
|
|
+ unsigned long long w : 1; /* Wait State */
|
|
|
+ unsigned long long p : 1; /* Problem State */
|
|
|
+ unsigned long long as : 2; /* Address Space Control */
|
|
|
+ unsigned long long cc : 2; /* Condition Code */
|
|
|
+ unsigned long long pm : 4; /* Program Mask */
|
|
|
+ unsigned long long ri : 1; /* Runtime Instrumentation */
|
|
|
+ unsigned long long : 6;
|
|
|
+ unsigned long long eaba : 2; /* Addressing Mode */
|
|
|
+#ifdef CONFIG_64BIT
|
|
|
+ unsigned long long : 31;
|
|
|
+ unsigned long long ia : 64;/* Instruction Address */
|
|
|
+#else
|
|
|
+ unsigned long long ia : 31;/* Instruction Address */
|
|
|
+#endif
|
|
|
+};
|
|
|
+
|
|
|
+enum {
|
|
|
+ PSW_AMODE_24BIT = 0,
|
|
|
+ PSW_AMODE_31BIT = 1,
|
|
|
+ PSW_AMODE_64BIT = 3
|
|
|
+};
|
|
|
+
|
|
|
+enum {
|
|
|
+ PSW_AS_PRIMARY = 0,
|
|
|
+ PSW_AS_ACCREG = 1,
|
|
|
+ PSW_AS_SECONDARY = 2,
|
|
|
+ PSW_AS_HOME = 3
|
|
|
+};
|
|
|
+
|
|
|
+#define psw_bits(__psw) (*({ \
|
|
|
+ typecheck(psw_t, __psw); \
|
|
|
+ &(*(struct psw_bits *)(&(__psw))); \
|
|
|
+}))
|
|
|
+
|
|
|
/*
|
|
|
* The pt_regs struct defines the way the registers are stored on
|
|
|
* the stack during a system call.
|