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@@ -31,6 +31,11 @@
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#define BM_USBPHY_CTRL_SFTRST BIT(31)
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#define BM_USBPHY_CTRL_CLKGATE BIT(30)
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+#define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
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+#define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
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+#define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
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+#define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
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+#define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
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#define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
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#define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
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#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
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@@ -96,9 +101,18 @@ static int mxs_phy_hw_init(struct mxs_phy *mxs_phy)
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/* Power up the PHY */
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writel(0, base + HW_USBPHY_PWD);
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- /* enable FS/LS device */
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- writel(BM_USBPHY_CTRL_ENUTMILEVEL2 |
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- BM_USBPHY_CTRL_ENUTMILEVEL3,
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+ /*
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+ * USB PHY Ctrl Setting
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+ * - Auto clock/power on
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+ * - Enable full/low speed support
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+ */
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+ writel(BM_USBPHY_CTRL_ENAUTOSET_USBCLKS |
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+ BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE |
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+ BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD |
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+ BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE |
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+ BM_USBPHY_CTRL_ENAUTO_PWRON_PLL |
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+ BM_USBPHY_CTRL_ENUTMILEVEL2 |
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+ BM_USBPHY_CTRL_ENUTMILEVEL3,
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base + HW_USBPHY_CTRL_SET);
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return 0;
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