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@@ -740,6 +740,17 @@ struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
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}
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EXPORT_SYMBOL(pci_add_new_bus);
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+static void pci_enable_crs(struct pci_dev *pdev)
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+{
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+ u16 root_cap = 0;
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+
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+ /* Enable CRS Software Visibility if supported */
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+ pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
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+ if (root_cap & PCI_EXP_RTCAP_CRSVIS)
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+ pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
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+ PCI_EXP_RTCTL_CRSSVE);
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+}
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+
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/*
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* If it's a bridge, configure it and scan the bus behind it.
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* For CardBus bridges, we don't scan behind as the devices will
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@@ -787,6 +798,8 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
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bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
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+ pci_enable_crs(dev);
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+
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if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
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!is_cardbus && !broken) {
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unsigned int cmax;
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@@ -1292,8 +1305,13 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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*l == 0x0000ffff || *l == 0xffff0000)
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return false;
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- /* Configuration request Retry Status */
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- while (*l == 0xffff0001) {
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+ /*
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+ * Configuration Request Retry Status. Some root ports return the
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+ * actual device ID instead of the synthetic ID (0xFFFF) required
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+ * by the PCIe spec. Ignore the device ID and only check for
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+ * (vendor id == 1).
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+ */
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+ while ((*l & 0xffff) == 0x0001) {
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if (!crs_timeout)
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return false;
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