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@@ -830,6 +830,9 @@ struct amdgpu_ring {
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/* PTBs (Page Table Blocks) need to be aligned to 32K */
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#define AMDGPU_VM_PTB_ALIGN_SIZE 32768
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+/* LOG2 number of continuous pages for the fragment field */
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+#define AMDGPU_LOG2_PAGES_PER_FRAG 4
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+
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#define AMDGPU_PTE_VALID (1 << 0)
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#define AMDGPU_PTE_SYSTEM (1 << 1)
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#define AMDGPU_PTE_SNOOPED (1 << 2)
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@@ -840,10 +843,7 @@ struct amdgpu_ring {
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#define AMDGPU_PTE_READABLE (1 << 5)
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#define AMDGPU_PTE_WRITEABLE (1 << 6)
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-/* PTE (Page Table Entry) fragment field for different page sizes */
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-#define AMDGPU_PTE_FRAG_4KB (0 << 7)
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-#define AMDGPU_PTE_FRAG_64KB (4 << 7)
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-#define AMDGPU_LOG2_PAGES_PER_FRAG 4
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+#define AMDGPU_PTE_FRAG(x) ((x & 0x1f) << 7)
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/* How to programm VM fault handling */
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#define AMDGPU_VM_FAULT_STOP_NEVER 0
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