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@@ -939,45 +939,46 @@ static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
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int happened, j;
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u32 unknown_mask;
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u32 irq_flags;
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+ int k = IRG_FLAGS_OFFSET + 5;
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if (g_spi.has_thrpt_enh) {
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ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
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int_status);
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- } else {
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- ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
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- &byte_cnt);
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- if (!ret) {
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- dev_err(&spi->dev,
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- "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
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- goto _fail_;
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- }
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- tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
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+ return ret;
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+ }
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+ ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
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+ if (!ret) {
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+ dev_err(&spi->dev,
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+ "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
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+ goto _fail_;
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+ }
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+ tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
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- j = 0;
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- do {
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- happened = 0;
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+ j = 0;
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+ do {
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+ happened = 0;
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- wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
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- tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
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+ wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
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+ tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
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- if (g_spi.nint > 5) {
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- wilc_spi_read_reg(wilc, 0x1a94,
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- &irq_flags);
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- tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
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- }
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+ if (g_spi.nint > 5) {
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+ wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
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+ tmp |= (((irq_flags >> 0) & 0x7) << k);
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+ }
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- unknown_mask = ~((1ul << g_spi.nint) - 1);
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+ unknown_mask = ~((1ul << g_spi.nint) - 1);
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- if ((tmp >> IRG_FLAGS_OFFSET) & unknown_mask) {
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- dev_err(&spi->dev, "Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unknown_mask);
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- happened = 1;
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- }
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+ if ((tmp >> IRG_FLAGS_OFFSET) & unknown_mask) {
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+ dev_err(&spi->dev,
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+ "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
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+ j, tmp, unknown_mask);
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+ happened = 1;
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+ }
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- j++;
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- } while (happened);
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+ j++;
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+ } while (happened);
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- *int_status = tmp;
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- }
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+ *int_status = tmp;
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_fail_:
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return ret;
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