|
@@ -0,0 +1,22 @@
|
|
|
|
+Rockchip specific extensions to the Analogix Display Port PHY
|
|
|
|
+------------------------------------
|
|
|
|
+
|
|
|
|
+Required properties:
|
|
|
|
+- compatible : should be one of the following supported values:
|
|
|
|
+ - "rockchip.rk3288-dp-phy"
|
|
|
|
+- clocks: from common clock binding: handle to dp clock.
|
|
|
|
+ of memory mapped region.
|
|
|
|
+- clock-names: from common clock binding:
|
|
|
|
+ Required elements: "24m"
|
|
|
|
+- rockchip,grf: phandle to the syscon managing the "general register files"
|
|
|
|
+- #phy-cells : from the generic PHY bindings, must be 0;
|
|
|
|
+
|
|
|
|
+Example:
|
|
|
|
+
|
|
|
|
+edp_phy: edp-phy {
|
|
|
|
+ compatible = "rockchip,rk3288-dp-phy";
|
|
|
|
+ rockchip,grf = <&grf>;
|
|
|
|
+ clocks = <&cru SCLK_EDP_24M>;
|
|
|
|
+ clock-names = "24m";
|
|
|
|
+ #phy-cells = <0>;
|
|
|
|
+};
|