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@@ -68,6 +68,9 @@
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static struct omap_dm_timer clkev;
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static struct clock_event_device clockevent_gpt;
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+/* Clockevent hwmod for am335x and am437x suspend */
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+static struct omap_hwmod *clockevent_gpt_hwmod;
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+
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#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
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static unsigned long arch_timer_freq;
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@@ -125,6 +128,23 @@ static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
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return 0;
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}
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+static void omap_clkevt_idle(struct clock_event_device *unused)
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+{
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+ if (!clockevent_gpt_hwmod)
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+ return;
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+
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+ omap_hwmod_idle(clockevent_gpt_hwmod);
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+}
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+
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+static void omap_clkevt_unidle(struct clock_event_device *unused)
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+{
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+ if (!clockevent_gpt_hwmod)
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+ return;
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+
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+ omap_hwmod_enable(clockevent_gpt_hwmod);
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+ __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
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+}
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+
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static struct clock_event_device clockevent_gpt = {
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.features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT,
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@@ -358,6 +378,14 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
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3, /* Timer internal resynch latency */
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0xffffffff);
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+ if (soc_is_am33xx() || soc_is_am43xx()) {
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+ clockevent_gpt.suspend = omap_clkevt_idle;
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+ clockevent_gpt.resume = omap_clkevt_unidle;
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+
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+ clockevent_gpt_hwmod =
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+ omap_hwmod_lookup(clockevent_gpt.name);
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+ }
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+
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pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
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clkev.rate);
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}
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