|
@@ -569,7 +569,7 @@
|
|
#define EXYNOS_CIIMGEFF_FIN_EMBOSSING (4 << 26)
|
|
#define EXYNOS_CIIMGEFF_FIN_EMBOSSING (4 << 26)
|
|
#define EXYNOS_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
|
|
#define EXYNOS_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
|
|
#define EXYNOS_CIIMGEFF_FIN_MASK (7 << 26)
|
|
#define EXYNOS_CIIMGEFF_FIN_MASK (7 << 26)
|
|
-#define EXYNOS_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0))
|
|
|
|
|
|
+#define EXYNOS_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | (0xff << 0))
|
|
|
|
|
|
/* Real input DMA size register */
|
|
/* Real input DMA size register */
|
|
#define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31)
|
|
#define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31)
|