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@@ -23,14 +23,7 @@
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#define CPU_MASK 0xff0ffff0
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#define CPU_CORTEX_A9 0x410fc090
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- /*
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- * The following code is located into the .data section. This is to
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- * allow l2x0_regs_phys to be accessed with a relative load while we
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- * can't rely on any MMU translation. We could have put l2x0_regs_phys
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- * in the .text section as well, but some setups might insist on it to
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- * be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
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- */
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- .data
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+ .text
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.align
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/*
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@@ -69,10 +62,12 @@ ENTRY(exynos_cpu_resume_ns)
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cmp r0, r1
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bne skip_cp15
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- adr r0, cp15_save_power
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+ adr r0, _cp15_save_power
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ldr r1, [r0]
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- adr r0, cp15_save_diag
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+ ldr r1, [r0, r1]
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+ adr r0, _cp15_save_diag
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ldr r2, [r0]
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+ ldr r2, [r0, r2]
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mov r0, #SMC_CMD_C15RESUME
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dsb
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smc #0
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@@ -118,14 +113,20 @@ skip_l2x0:
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skip_cp15:
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b cpu_resume
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ENDPROC(exynos_cpu_resume_ns)
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+
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+ .align
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+_cp15_save_power:
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+ .long cp15_save_power - .
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+_cp15_save_diag:
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+ .long cp15_save_diag - .
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+#ifdef CONFIG_CACHE_L2X0
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+1: .long l2x0_saved_regs - .
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+#endif /* CONFIG_CACHE_L2X0 */
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+
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+ .data
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.globl cp15_save_diag
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cp15_save_diag:
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.long 0 @ cp15 diagnostic
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.globl cp15_save_power
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cp15_save_power:
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.long 0 @ cp15 power control
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-
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-#ifdef CONFIG_CACHE_L2X0
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- .align
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-1: .long l2x0_saved_regs - .
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-#endif /* CONFIG_CACHE_L2X0 */
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