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@@ -77,8 +77,9 @@
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#define PCIE_SCRATCH_10_REG 0xCE8
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#define PCIE_SCRATCH_11_REG 0xCEC
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#define PCIE_SCRATCH_12_REG 0xCF0
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-#define PCIE_SCRATCH_13_REG 0xCF8
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-#define PCIE_SCRATCH_14_REG 0xCFC
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+#define PCIE_SCRATCH_13_REG 0xCF4
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+#define PCIE_SCRATCH_14_REG 0xCF8
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+#define PCIE_SCRATCH_15_REG 0xCFC
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#define PCIE_RD_DATA_PTR_Q0_Q1 0xC08C
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#define PCIE_WR_DATA_PTR_Q0_Q1 0xC05C
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@@ -217,8 +218,8 @@ static const struct mwifiex_pcie_card_reg mwifiex_reg_8897 = {
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.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
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.pfu_enabled = 1,
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.sleep_cookie = 0,
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- .fw_dump_ctrl = 0xcf4,
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- .fw_dump_start = 0xcf8,
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+ .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
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+ .fw_dump_start = PCIE_SCRATCH_14_REG,
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.fw_dump_end = 0xcff,
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.fw_dump_host_ready = 0xee,
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.fw_dump_read_done = 0xfe,
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@@ -254,8 +255,8 @@ static const struct mwifiex_pcie_card_reg mwifiex_reg_8997 = {
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.ring_tx_start_ptr = MWIFIEX_BD_FLAG_TX_START_PTR,
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.pfu_enabled = 1,
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.sleep_cookie = 0,
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- .fw_dump_ctrl = 0xcf4,
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- .fw_dump_start = 0xcf8,
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+ .fw_dump_ctrl = PCIE_SCRATCH_13_REG,
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+ .fw_dump_start = PCIE_SCRATCH_14_REG,
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.fw_dump_end = 0xcff,
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.fw_dump_host_ready = 0xcc,
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.fw_dump_read_done = 0xdd,
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