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@@ -946,6 +946,8 @@ static const char *rtc_parents[4] = {
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static const char *lcd_parent[1] = { "pllsai-r-div" };
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+static const char *i2s_parents[2] = { "plli2s-r", NULL };
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+
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struct stm32_aux_clk {
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int idx;
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const char *name;
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@@ -975,6 +977,12 @@ static const struct stm32_aux_clk stm32f429_aux_clk[] = {
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STM32F4_RCC_APB2ENR, 26,
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CLK_SET_RATE_PARENT
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},
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+ {
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+ CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
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+ STM32F4_RCC_CFGR, 23, 1,
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+ NO_GATE, 0,
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+ CLK_SET_RATE_PARENT
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+ },
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};
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static const struct stm32f4_clk_data stm32f429_clk_data = {
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@@ -1069,7 +1077,7 @@ fail:
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static void __init stm32f4_rcc_init(struct device_node *np)
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{
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- const char *hse_clk;
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+ const char *hse_clk, *i2s_in_clk;
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int n;
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const struct of_device_id *match;
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const struct stm32f4_clk_data *data;
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@@ -1104,6 +1112,10 @@ static void __init stm32f4_rcc_init(struct device_node *np)
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hse_clk = of_clk_get_parent_name(np, 0);
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+ i2s_in_clk = of_clk_get_parent_name(np, 1);
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+
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+ i2s_parents[1] = i2s_in_clk;
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+
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clk_register_fixed_rate_with_accuracy(NULL, "hsi", NULL, 0,
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16000000, 160000);
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pllcfgr = readl(base + STM32F4_RCC_PLLCFGR);
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