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@@ -42,6 +42,8 @@
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#define QCA6174_HW_3_0_VERSION 0x05020000
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#define QCA6174_HW_3_0_VERSION 0x05020000
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#define QCA6174_HW_3_2_VERSION 0x05030000
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#define QCA6174_HW_3_2_VERSION 0x05030000
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+#define QCA9377_HW_1_1_DEV_VERSION 0x05020001
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+
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enum qca6174_pci_rev {
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enum qca6174_pci_rev {
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QCA6174_PCI_REV_1_1 = 0x11,
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QCA6174_PCI_REV_1_1 = 0x11,
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QCA6174_PCI_REV_1_3 = 0x13,
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QCA6174_PCI_REV_1_3 = 0x13,
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@@ -60,6 +62,10 @@ enum qca6174_chip_id_rev {
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QCA6174_HW_3_2_CHIP_ID_REV = 10,
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QCA6174_HW_3_2_CHIP_ID_REV = 10,
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};
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};
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+enum qca9377_chip_id_rev {
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+ QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
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+};
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+
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#define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
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#define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
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#define QCA6174_HW_2_1_FW_FILE "firmware.bin"
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#define QCA6174_HW_2_1_FW_FILE "firmware.bin"
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#define QCA6174_HW_2_1_OTP_FILE "otp.bin"
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#define QCA6174_HW_2_1_OTP_FILE "otp.bin"
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@@ -85,8 +91,6 @@ enum qca6174_chip_id_rev {
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#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
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#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
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/* QCA9377 1.0 definitions */
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/* QCA9377 1.0 definitions */
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-#define QCA9377_HW_1_0_DEV_VERSION 0x05020001
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-#define QCA9377_HW_1_0_CHIP_ID_REV 0x1
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#define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
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#define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
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#define QCA9377_HW_1_0_FW_FILE "firmware.bin"
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#define QCA9377_HW_1_0_FW_FILE "firmware.bin"
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#define QCA9377_HW_1_0_OTP_FILE "otp.bin"
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#define QCA9377_HW_1_0_OTP_FILE "otp.bin"
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