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@@ -120,10 +120,6 @@
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/*
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* FPU Status Register Values
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*/
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-/*
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- * Status Register Values
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- */
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-
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#define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
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#define FPU_CSR_COND 0x00800000 /* $fcc0 */
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#define FPU_CSR_COND0 0x00800000 /* $fcc0 */
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@@ -425,8 +421,6 @@
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/*
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* Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
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- *
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- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
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*/
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#define INTCTLB_IPFDC 23
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#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
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