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@@ -21,6 +21,7 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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+#include <linux/pm.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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@@ -28,19 +29,36 @@
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#include <asm/gpio.h>
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#include <asm/mach/irq.h>
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+#define OFF_MODE 1
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+
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+static LIST_HEAD(omap_gpio_list);
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+
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+struct gpio_regs {
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+ u32 irqenable1;
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+ u32 irqenable2;
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+ u32 wake_en;
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+ u32 ctrl;
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+ u32 oe;
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+ u32 leveldetect0;
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+ u32 leveldetect1;
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+ u32 risingdetect;
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+ u32 fallingdetect;
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+ u32 dataout;
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+ u32 debounce;
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+ u32 debounce_en;
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+};
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+
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struct gpio_bank {
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+ struct list_head node;
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unsigned long pbase;
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void __iomem *base;
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u16 irq;
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u16 virtual_irq_start;
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- int method;
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u32 suspend_wakeup;
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-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
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u32 saved_wakeup;
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-#endif
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u32 non_wakeup_gpios;
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u32 enabled_non_wakeup_gpios;
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-
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+ struct gpio_regs context;
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u32 saved_datain;
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u32 saved_fallingdetect;
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u32 saved_risingdetect;
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@@ -51,44 +69,27 @@ struct gpio_bank {
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struct clk *dbck;
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u32 mod_usage;
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u32 dbck_enable_mask;
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+ bool dbck_enabled;
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struct device *dev;
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+ bool is_mpuio;
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bool dbck_flag;
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+ bool loses_context;
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int stride;
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u32 width;
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+ int context_loss_count;
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+ u16 id;
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+ int power_mode;
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+ bool workaround_enabled;
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void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
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+ int (*get_context_loss_count)(struct device *dev);
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struct omap_gpio_reg_offs *regs;
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};
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-#ifdef CONFIG_ARCH_OMAP3
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-struct omap3_gpio_regs {
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- u32 irqenable1;
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- u32 irqenable2;
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- u32 wake_en;
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- u32 ctrl;
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- u32 oe;
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- u32 leveldetect0;
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- u32 leveldetect1;
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- u32 risingdetect;
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- u32 fallingdetect;
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- u32 dataout;
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-};
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-
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-static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
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-#endif
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-
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-/*
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- * TODO: Cleanup gpio_bank usage as it is having information
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- * related to all instances of the device
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- */
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-static struct gpio_bank *gpio_bank;
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-
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-/* TODO: Analyze removing gpio_bank_count usage from driver code */
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-int gpio_bank_count;
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-
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#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
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#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
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+#define GPIO_MOD_CTRL_BIT BIT(0)
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static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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{
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@@ -102,6 +103,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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else
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l &= ~(1 << gpio);
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__raw_writel(l, reg);
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+ bank->context.oe = l;
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}
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@@ -132,6 +134,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
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else
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l &= ~gpio_bit;
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__raw_writel(l, reg);
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+ bank->context.dataout = l;
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}
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static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
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@@ -160,6 +163,22 @@ static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
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__raw_writel(l, base + reg);
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}
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+static inline void _gpio_dbck_enable(struct gpio_bank *bank)
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+{
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+ if (bank->dbck_enable_mask && !bank->dbck_enabled) {
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+ clk_enable(bank->dbck);
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+ bank->dbck_enabled = true;
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+ }
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+}
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+
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+static inline void _gpio_dbck_disable(struct gpio_bank *bank)
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+{
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+ if (bank->dbck_enable_mask && bank->dbck_enabled) {
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+ clk_disable(bank->dbck);
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+ bank->dbck_enabled = false;
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+ }
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+}
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+
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/**
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* _set_gpio_debounce - low level gpio debounce time
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* @bank: the gpio bank we're acting upon
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@@ -188,70 +207,74 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
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l = GPIO_BIT(bank, gpio);
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+ clk_enable(bank->dbck);
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reg = bank->base + bank->regs->debounce;
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__raw_writel(debounce, reg);
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reg = bank->base + bank->regs->debounce_en;
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val = __raw_readl(reg);
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- if (debounce) {
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+ if (debounce)
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val |= l;
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- clk_enable(bank->dbck);
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- } else {
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+ else
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val &= ~l;
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- clk_disable(bank->dbck);
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- }
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bank->dbck_enable_mask = val;
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__raw_writel(val, reg);
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+ clk_disable(bank->dbck);
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+ /*
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+ * Enable debounce clock per module.
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+ * This call is mandatory because in omap_gpio_request() when
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+ * *_runtime_get_sync() is called, _gpio_dbck_enable() within
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+ * runtime callbck fails to turn on dbck because dbck_enable_mask
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+ * used within _gpio_dbck_enable() is still not initialized at
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+ * that point. Therefore we have to enable dbck here.
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+ */
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+ _gpio_dbck_enable(bank);
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+ if (bank->dbck_enable_mask) {
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+ bank->context.debounce = debounce;
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+ bank->context.debounce_en = val;
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+ }
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}
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-#ifdef CONFIG_ARCH_OMAP2PLUS
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-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
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+static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
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int trigger)
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{
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void __iomem *base = bank->base;
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u32 gpio_bit = 1 << gpio;
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- if (cpu_is_omap44xx()) {
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- _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
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- trigger & IRQ_TYPE_LEVEL_LOW);
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- _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
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- trigger & IRQ_TYPE_LEVEL_HIGH);
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- _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
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- trigger & IRQ_TYPE_EDGE_RISING);
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- _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
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- trigger & IRQ_TYPE_EDGE_FALLING);
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- } else {
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- _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
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- trigger & IRQ_TYPE_LEVEL_LOW);
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- _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
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- trigger & IRQ_TYPE_LEVEL_HIGH);
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- _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
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- trigger & IRQ_TYPE_EDGE_RISING);
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- _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
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- trigger & IRQ_TYPE_EDGE_FALLING);
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- }
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+ _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
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+ trigger & IRQ_TYPE_LEVEL_LOW);
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+ _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
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+ trigger & IRQ_TYPE_LEVEL_HIGH);
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+ _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
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+ trigger & IRQ_TYPE_EDGE_RISING);
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+ _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
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+ trigger & IRQ_TYPE_EDGE_FALLING);
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+
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+ bank->context.leveldetect0 =
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+ __raw_readl(bank->base + bank->regs->leveldetect0);
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+ bank->context.leveldetect1 =
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+ __raw_readl(bank->base + bank->regs->leveldetect1);
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+ bank->context.risingdetect =
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+ __raw_readl(bank->base + bank->regs->risingdetect);
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+ bank->context.fallingdetect =
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+ __raw_readl(bank->base + bank->regs->fallingdetect);
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+
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if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
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- if (cpu_is_omap44xx()) {
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- _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit,
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- trigger != 0);
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- } else {
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- /*
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- * GPIO wakeup request can only be generated on edge
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- * transitions
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- */
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- if (trigger & IRQ_TYPE_EDGE_BOTH)
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- __raw_writel(1 << gpio, bank->base
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- + OMAP24XX_GPIO_SETWKUENA);
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- else
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- __raw_writel(1 << gpio, bank->base
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- + OMAP24XX_GPIO_CLEARWKUENA);
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- }
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+ _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
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+ bank->context.wake_en =
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+ __raw_readl(bank->base + bank->regs->wkup_en);
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}
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+
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/* This part needs to be executed always for OMAP{34xx, 44xx} */
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- if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
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- (bank->non_wakeup_gpios & gpio_bit)) {
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+ if (!bank->regs->irqctrl) {
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+ /* On omap24xx proceed only when valid GPIO bit is set */
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+ if (bank->non_wakeup_gpios) {
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+ if (!(bank->non_wakeup_gpios & gpio_bit))
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+ goto exit;
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+ }
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+
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/*
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* Log the edge gpio and manually trigger the IRQ
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* after resume if the input level changes
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@@ -264,17 +287,11 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
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bank->enabled_non_wakeup_gpios &= ~gpio_bit;
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}
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- if (cpu_is_omap44xx()) {
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- bank->level_mask =
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- __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
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- __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
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- } else {
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- bank->level_mask =
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- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
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- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
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- }
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+exit:
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+ bank->level_mask =
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+ __raw_readl(bank->base + bank->regs->leveldetect0) |
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+ __raw_readl(bank->base + bank->regs->leveldetect1);
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}
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-#endif
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#ifdef CONFIG_ARCH_OMAP1
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/*
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@@ -286,23 +303,10 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
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void __iomem *reg = bank->base;
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u32 l = 0;
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- switch (bank->method) {
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- case METHOD_MPUIO:
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- reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
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- break;
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-#ifdef CONFIG_ARCH_OMAP15XX
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- case METHOD_GPIO_1510:
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- reg += OMAP1510_GPIO_INT_CONTROL;
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- break;
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-#endif
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-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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- case METHOD_GPIO_7XX:
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- reg += OMAP7XX_GPIO_INT_CONTROL;
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- break;
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-#endif
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- default:
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+ if (!bank->regs->irqctrl)
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return;
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- }
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+
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+ reg += bank->regs->irqctrl;
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l = __raw_readl(reg);
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if ((l >> gpio) & 1)
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@@ -312,31 +316,21 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
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__raw_writel(l, reg);
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}
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+#else
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+static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
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#endif
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static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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{
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void __iomem *reg = bank->base;
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+ void __iomem *base = bank->base;
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u32 l = 0;
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- switch (bank->method) {
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-#ifdef CONFIG_ARCH_OMAP1
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- case METHOD_MPUIO:
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- reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
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- l = __raw_readl(reg);
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- if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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- bank->toggle_mask |= 1 << gpio;
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- if (trigger & IRQ_TYPE_EDGE_RISING)
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- l |= 1 << gpio;
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- else if (trigger & IRQ_TYPE_EDGE_FALLING)
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- l &= ~(1 << gpio);
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- else
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- goto bad;
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- break;
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-#endif
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-#ifdef CONFIG_ARCH_OMAP15XX
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- case METHOD_GPIO_1510:
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- reg += OMAP1510_GPIO_INT_CONTROL;
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+ if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
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+ set_gpio_trigger(bank, gpio, trigger);
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+ } else if (bank->regs->irqctrl) {
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+ reg += bank->regs->irqctrl;
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+
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l = __raw_readl(reg);
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if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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bank->toggle_mask |= 1 << gpio;
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@@ -345,15 +339,15 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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else if (trigger & IRQ_TYPE_EDGE_FALLING)
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l &= ~(1 << gpio);
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else
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- goto bad;
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- break;
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-#endif
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-#ifdef CONFIG_ARCH_OMAP16XX
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- case METHOD_GPIO_1610:
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+ return -EINVAL;
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+
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+ __raw_writel(l, reg);
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+ } else if (bank->regs->edgectrl1) {
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if (gpio & 0x08)
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- reg += OMAP1610_GPIO_EDGE_CTRL2;
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+ reg += bank->regs->edgectrl2;
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else
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- reg += OMAP1610_GPIO_EDGE_CTRL1;
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+ reg += bank->regs->edgectrl1;
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+
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gpio &= 0x07;
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l = __raw_readl(reg);
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l &= ~(3 << (gpio << 1));
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@@ -361,40 +355,14 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
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l |= 2 << (gpio << 1);
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if (trigger & IRQ_TYPE_EDGE_FALLING)
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l |= 1 << (gpio << 1);
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- if (trigger)
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- /* Enable wake-up during idle for dynamic tick */
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- __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
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- else
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- __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
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- break;
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-#endif
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-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
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- case METHOD_GPIO_7XX:
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- reg += OMAP7XX_GPIO_INT_CONTROL;
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- l = __raw_readl(reg);
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- if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
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- bank->toggle_mask |= 1 << gpio;
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- if (trigger & IRQ_TYPE_EDGE_RISING)
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- l |= 1 << gpio;
|
|
|
- else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
|
|
- l &= ~(1 << gpio);
|
|
|
- else
|
|
|
- goto bad;
|
|
|
- break;
|
|
|
-#endif
|
|
|
-#ifdef CONFIG_ARCH_OMAP2PLUS
|
|
|
- case METHOD_GPIO_24XX:
|
|
|
- case METHOD_GPIO_44XX:
|
|
|
- set_24xx_gpio_triggering(bank, gpio, trigger);
|
|
|
- return 0;
|
|
|
-#endif
|
|
|
- default:
|
|
|
- goto bad;
|
|
|
+
|
|
|
+ /* Enable wake-up during idle for dynamic tick */
|
|
|
+ _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
|
|
|
+ bank->context.wake_en =
|
|
|
+ __raw_readl(bank->base + bank->regs->wkup_en);
|
|
|
+ __raw_writel(l, reg);
|
|
|
}
|
|
|
- __raw_writel(l, reg);
|
|
|
return 0;
|
|
|
-bad:
|
|
|
- return -EINVAL;
|
|
|
}
|
|
|
|
|
|
static int gpio_irq_type(struct irq_data *d, unsigned type)
|
|
|
@@ -412,12 +380,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
|
|
|
if (type & ~IRQ_TYPE_SENSE_MASK)
|
|
|
return -EINVAL;
|
|
|
|
|
|
- /* OMAP1 allows only only edge triggering */
|
|
|
- if (!cpu_class_is_omap2()
|
|
|
- && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
|
|
|
+ bank = irq_data_get_irq_chip_data(d);
|
|
|
+
|
|
|
+ if (!bank->regs->leveldetect0 &&
|
|
|
+ (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
|
|
|
return -EINVAL;
|
|
|
|
|
|
- bank = irq_data_get_irq_chip_data(d);
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
@@ -484,6 +452,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
}
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
+ bank->context.irqenable1 = l;
|
|
|
}
|
|
|
|
|
|
static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
@@ -504,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
}
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
+ bank->context.irqenable1 = l;
|
|
|
}
|
|
|
|
|
|
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
|
|
|
@@ -567,38 +537,39 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
|
|
unsigned long flags;
|
|
|
|
|
|
- spin_lock_irqsave(&bank->lock, flags);
|
|
|
+ /*
|
|
|
+ * If this is the first gpio_request for the bank,
|
|
|
+ * enable the bank module.
|
|
|
+ */
|
|
|
+ if (!bank->mod_usage)
|
|
|
+ pm_runtime_get_sync(bank->dev);
|
|
|
|
|
|
+ spin_lock_irqsave(&bank->lock, flags);
|
|
|
/* Set trigger to none. You need to enable the desired trigger with
|
|
|
* request_irq() or set_irq_type().
|
|
|
*/
|
|
|
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
|
|
|
|
|
|
-#ifdef CONFIG_ARCH_OMAP15XX
|
|
|
- if (bank->method == METHOD_GPIO_1510) {
|
|
|
- void __iomem *reg;
|
|
|
+ if (bank->regs->pinctrl) {
|
|
|
+ void __iomem *reg = bank->base + bank->regs->pinctrl;
|
|
|
|
|
|
/* Claim the pin for MPU */
|
|
|
- reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
|
|
|
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
|
|
|
}
|
|
|
-#endif
|
|
|
- if (!cpu_class_is_omap1()) {
|
|
|
- if (!bank->mod_usage) {
|
|
|
- void __iomem *reg = bank->base;
|
|
|
- u32 ctrl;
|
|
|
-
|
|
|
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
|
- reg += OMAP24XX_GPIO_CTRL;
|
|
|
- else if (cpu_is_omap44xx())
|
|
|
- reg += OMAP4_GPIO_CTRL;
|
|
|
- ctrl = __raw_readl(reg);
|
|
|
- /* Module is enabled, clocks are not gated */
|
|
|
- ctrl &= 0xFFFFFFFE;
|
|
|
- __raw_writel(ctrl, reg);
|
|
|
- }
|
|
|
- bank->mod_usage |= 1 << offset;
|
|
|
+
|
|
|
+ if (bank->regs->ctrl && !bank->mod_usage) {
|
|
|
+ void __iomem *reg = bank->base + bank->regs->ctrl;
|
|
|
+ u32 ctrl;
|
|
|
+
|
|
|
+ ctrl = __raw_readl(reg);
|
|
|
+ /* Module is enabled, clocks are not gated */
|
|
|
+ ctrl &= ~GPIO_MOD_CTRL_BIT;
|
|
|
+ __raw_writel(ctrl, reg);
|
|
|
+ bank->context.ctrl = ctrl;
|
|
|
}
|
|
|
+
|
|
|
+ bank->mod_usage |= 1 << offset;
|
|
|
+
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
return 0;
|
|
|
@@ -607,48 +578,40 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
|
|
|
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
|
|
|
{
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
|
|
+ void __iomem *base = bank->base;
|
|
|
unsigned long flags;
|
|
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
-#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
- if (bank->method == METHOD_GPIO_1610) {
|
|
|
- /* Disable wake-up during idle for dynamic tick */
|
|
|
- void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
- __raw_writel(1 << offset, reg);
|
|
|
- }
|
|
|
-#endif
|
|
|
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
|
- if (bank->method == METHOD_GPIO_24XX) {
|
|
|
- /* Disable wake-up during idle for dynamic tick */
|
|
|
- void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
- __raw_writel(1 << offset, reg);
|
|
|
- }
|
|
|
-#endif
|
|
|
-#ifdef CONFIG_ARCH_OMAP4
|
|
|
- if (bank->method == METHOD_GPIO_44XX) {
|
|
|
+
|
|
|
+ if (bank->regs->wkup_en) {
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
|
- void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
- __raw_writel(1 << offset, reg);
|
|
|
+ _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
|
|
|
+ bank->context.wake_en =
|
|
|
+ __raw_readl(bank->base + bank->regs->wkup_en);
|
|
|
}
|
|
|
-#endif
|
|
|
- if (!cpu_class_is_omap1()) {
|
|
|
- bank->mod_usage &= ~(1 << offset);
|
|
|
- if (!bank->mod_usage) {
|
|
|
- void __iomem *reg = bank->base;
|
|
|
- u32 ctrl;
|
|
|
-
|
|
|
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
|
- reg += OMAP24XX_GPIO_CTRL;
|
|
|
- else if (cpu_is_omap44xx())
|
|
|
- reg += OMAP4_GPIO_CTRL;
|
|
|
- ctrl = __raw_readl(reg);
|
|
|
- /* Module is disabled, clocks are gated */
|
|
|
- ctrl |= 1;
|
|
|
- __raw_writel(ctrl, reg);
|
|
|
- }
|
|
|
+
|
|
|
+ bank->mod_usage &= ~(1 << offset);
|
|
|
+
|
|
|
+ if (bank->regs->ctrl && !bank->mod_usage) {
|
|
|
+ void __iomem *reg = bank->base + bank->regs->ctrl;
|
|
|
+ u32 ctrl;
|
|
|
+
|
|
|
+ ctrl = __raw_readl(reg);
|
|
|
+ /* Module is disabled, clocks are gated */
|
|
|
+ ctrl |= GPIO_MOD_CTRL_BIT;
|
|
|
+ __raw_writel(ctrl, reg);
|
|
|
+ bank->context.ctrl = ctrl;
|
|
|
}
|
|
|
+
|
|
|
_reset_gpio(bank, bank->chip.base + offset);
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * If this is the last gpio to be freed in the bank,
|
|
|
+ * disable the bank module.
|
|
|
+ */
|
|
|
+ if (!bank->mod_usage)
|
|
|
+ pm_runtime_put(bank->dev);
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
@@ -674,6 +637,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
|
|
|
|
bank = irq_get_handler_data(irq);
|
|
|
isr_reg = bank->base + bank->regs->irqstatus;
|
|
|
+ pm_runtime_get_sync(bank->dev);
|
|
|
|
|
|
if (WARN_ON(!isr_reg))
|
|
|
goto exit;
|
|
|
@@ -685,12 +649,8 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
|
enabled = _get_gpio_irqbank_mask(bank);
|
|
|
isr_saved = isr = __raw_readl(isr_reg) & enabled;
|
|
|
|
|
|
- if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
|
|
|
- isr &= 0x0000ffff;
|
|
|
-
|
|
|
- if (cpu_class_is_omap2()) {
|
|
|
+ if (bank->level_mask)
|
|
|
level_mask = bank->level_mask & enabled;
|
|
|
- }
|
|
|
|
|
|
/* clear edge sensitive interrupts before handler(s) are
|
|
|
called so that we don't miss any interrupt occurred while
|
|
|
@@ -718,7 +678,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
|
if (!(isr & 1))
|
|
|
continue;
|
|
|
|
|
|
-#ifdef CONFIG_ARCH_OMAP1
|
|
|
/*
|
|
|
* Some chips can't respond to both rising and falling
|
|
|
* at the same time. If this irq was requested with
|
|
|
@@ -728,7 +687,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
|
*/
|
|
|
if (bank->toggle_mask & (1 << gpio_index))
|
|
|
_toggle_gpio_edge_triggering(bank, gpio_index);
|
|
|
-#endif
|
|
|
|
|
|
generic_handle_irq(gpio_irq);
|
|
|
}
|
|
|
@@ -740,6 +698,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
|
|
exit:
|
|
|
if (!unmasked)
|
|
|
chained_irq_exit(chip, desc);
|
|
|
+ pm_runtime_put(bank->dev);
|
|
|
}
|
|
|
|
|
|
static void gpio_irq_shutdown(struct irq_data *d)
|
|
|
@@ -808,14 +767,6 @@ static struct irq_chip gpio_irq_chip = {
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
|
-#ifdef CONFIG_ARCH_OMAP1
|
|
|
-
|
|
|
-#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
|
|
|
-
|
|
|
-#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
-
|
|
|
-#include <linux/platform_device.h>
|
|
|
-
|
|
|
static int omap_mpuio_suspend_noirq(struct device *dev)
|
|
|
{
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
@@ -869,32 +820,16 @@ static struct platform_device omap_mpuio_device = {
|
|
|
/* could list the /proc/iomem resources */
|
|
|
};
|
|
|
|
|
|
-static inline void mpuio_init(void)
|
|
|
+static inline void mpuio_init(struct gpio_bank *bank)
|
|
|
{
|
|
|
- struct gpio_bank *bank = &gpio_bank[0];
|
|
|
platform_set_drvdata(&omap_mpuio_device, bank);
|
|
|
|
|
|
if (platform_driver_register(&omap_mpuio_driver) == 0)
|
|
|
(void) platform_device_register(&omap_mpuio_device);
|
|
|
}
|
|
|
|
|
|
-#else
|
|
|
-static inline void mpuio_init(void) {}
|
|
|
-#endif /* 16xx */
|
|
|
-
|
|
|
-#else
|
|
|
-
|
|
|
-#define bank_is_mpuio(bank) 0
|
|
|
-static inline void mpuio_init(void) {}
|
|
|
-
|
|
|
-#endif
|
|
|
-
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
|
-/* REVISIT these are stupid implementations! replace by ones that
|
|
|
- * don't switch on METHOD_* and which mostly avoid spinlocks
|
|
|
- */
|
|
|
-
|
|
|
static int gpio_input(struct gpio_chip *chip, unsigned offset)
|
|
|
{
|
|
|
struct gpio_bank *bank;
|
|
|
@@ -1007,71 +942,32 @@ static void __init omap_gpio_show_rev(struct gpio_bank *bank)
|
|
|
*/
|
|
|
static struct lock_class_key gpio_lock_class;
|
|
|
|
|
|
-static inline int init_gpio_info(struct platform_device *pdev)
|
|
|
+static void omap_gpio_mod_init(struct gpio_bank *bank)
|
|
|
{
|
|
|
- /* TODO: Analyze removing gpio_bank_count usage from driver code */
|
|
|
- gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
|
|
|
- GFP_KERNEL);
|
|
|
- if (!gpio_bank) {
|
|
|
- dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
|
|
|
- return -ENOMEM;
|
|
|
- }
|
|
|
- return 0;
|
|
|
-}
|
|
|
+ void __iomem *base = bank->base;
|
|
|
+ u32 l = 0xffffffff;
|
|
|
|
|
|
-/* TODO: Cleanup cpu_is_* checks */
|
|
|
-static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
|
|
|
-{
|
|
|
- if (cpu_class_is_omap2()) {
|
|
|
- if (cpu_is_omap44xx()) {
|
|
|
- __raw_writel(0xffffffff, bank->base +
|
|
|
- OMAP4_GPIO_IRQSTATUSCLR0);
|
|
|
- __raw_writel(0x00000000, bank->base +
|
|
|
- OMAP4_GPIO_DEBOUNCENABLE);
|
|
|
- /* Initialize interface clk ungated, module enabled */
|
|
|
- __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
|
|
|
- } else if (cpu_is_omap34xx()) {
|
|
|
- __raw_writel(0x00000000, bank->base +
|
|
|
- OMAP24XX_GPIO_IRQENABLE1);
|
|
|
- __raw_writel(0xffffffff, bank->base +
|
|
|
- OMAP24XX_GPIO_IRQSTATUS1);
|
|
|
- __raw_writel(0x00000000, bank->base +
|
|
|
- OMAP24XX_GPIO_DEBOUNCE_EN);
|
|
|
-
|
|
|
- /* Initialize interface clk ungated, module enabled */
|
|
|
- __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
- } else if (cpu_is_omap24xx()) {
|
|
|
- static const u32 non_wakeup_gpios[] = {
|
|
|
- 0xe203ffc0, 0x08700040
|
|
|
- };
|
|
|
- if (id < ARRAY_SIZE(non_wakeup_gpios))
|
|
|
- bank->non_wakeup_gpios = non_wakeup_gpios[id];
|
|
|
- }
|
|
|
- } else if (cpu_class_is_omap1()) {
|
|
|
- if (bank_is_mpuio(bank))
|
|
|
- __raw_writew(0xffff, bank->base +
|
|
|
- OMAP_MPUIO_GPIO_MASKIT / bank->stride);
|
|
|
- if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
|
|
|
- __raw_writew(0xffff, bank->base
|
|
|
- + OMAP1510_GPIO_INT_MASK);
|
|
|
- __raw_writew(0x0000, bank->base
|
|
|
- + OMAP1510_GPIO_INT_STATUS);
|
|
|
- }
|
|
|
- if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
|
|
|
- __raw_writew(0x0000, bank->base
|
|
|
- + OMAP1610_GPIO_IRQENABLE1);
|
|
|
- __raw_writew(0xffff, bank->base
|
|
|
- + OMAP1610_GPIO_IRQSTATUS1);
|
|
|
- __raw_writew(0x0014, bank->base
|
|
|
- + OMAP1610_GPIO_SYSCONFIG);
|
|
|
- }
|
|
|
- if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
|
|
|
- __raw_writel(0xffffffff, bank->base
|
|
|
- + OMAP7XX_GPIO_INT_MASK);
|
|
|
- __raw_writel(0x00000000, bank->base
|
|
|
- + OMAP7XX_GPIO_INT_STATUS);
|
|
|
- }
|
|
|
+ if (bank->width == 16)
|
|
|
+ l = 0xffff;
|
|
|
+
|
|
|
+ if (bank->is_mpuio) {
|
|
|
+ __raw_writel(l, bank->base + bank->regs->irqenable);
|
|
|
+ return;
|
|
|
}
|
|
|
+
|
|
|
+ _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
|
|
|
+ _gpio_rmw(base, bank->regs->irqstatus, l,
|
|
|
+ bank->regs->irqenable_inv == false);
|
|
|
+ _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
|
|
|
+ _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
|
|
|
+ if (bank->regs->debounce_en)
|
|
|
+ _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
|
|
|
+
|
|
|
+ /* Save OE default value (0xffffffff) in the context */
|
|
|
+ bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
|
|
|
+ /* Initialize interface clk ungated, module enabled */
|
|
|
+ if (bank->regs->ctrl)
|
|
|
+ _gpio_rmw(base, bank->regs->ctrl, 0, 1);
|
|
|
}
|
|
|
|
|
|
static __init void
|
|
|
@@ -1094,8 +990,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
|
|
|
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
|
|
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
|
|
ct->chip.irq_set_type = gpio_irq_type;
|
|
|
- /* REVISIT: assuming only 16xx supports MPUIO wake events */
|
|
|
- if (cpu_is_omap16xx())
|
|
|
+
|
|
|
+ if (bank->regs->wkup_en)
|
|
|
ct->chip.irq_set_wake = gpio_wake_enable,
|
|
|
|
|
|
ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
|
|
|
@@ -1108,7 +1004,6 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
|
|
|
int j;
|
|
|
static int gpio;
|
|
|
|
|
|
- bank->mod_usage = 0;
|
|
|
/*
|
|
|
* REVISIT eventually switch from OMAP-specific gpio structs
|
|
|
* over to the generic ones
|
|
|
@@ -1121,11 +1016,10 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
|
|
|
bank->chip.set_debounce = gpio_debounce;
|
|
|
bank->chip.set = gpio_set;
|
|
|
bank->chip.to_irq = gpio_2irq;
|
|
|
- if (bank_is_mpuio(bank)) {
|
|
|
+ if (bank->is_mpuio) {
|
|
|
bank->chip.label = "mpuio";
|
|
|
-#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
- bank->chip.dev = &omap_mpuio_device.dev;
|
|
|
-#endif
|
|
|
+ if (bank->regs->wkup_en)
|
|
|
+ bank->chip.dev = &omap_mpuio_device.dev;
|
|
|
bank->chip.base = OMAP_MPUIO(0);
|
|
|
} else {
|
|
|
bank->chip.label = "gpio";
|
|
|
@@ -1140,7 +1034,7 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
|
|
|
j < bank->virtual_irq_start + bank->width; j++) {
|
|
|
irq_set_lockdep_class(j, &gpio_lock_class);
|
|
|
irq_set_chip_data(j, bank);
|
|
|
- if (bank_is_mpuio(bank)) {
|
|
|
+ if (bank->is_mpuio) {
|
|
|
omap_mpuio_alloc_gc(bank, j, bank->width);
|
|
|
} else {
|
|
|
irq_set_chip(j, &gpio_irq_chip);
|
|
|
@@ -1154,42 +1048,44 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
|
|
|
|
|
|
static int __devinit omap_gpio_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
- static int gpio_init_done;
|
|
|
struct omap_gpio_platform_data *pdata;
|
|
|
struct resource *res;
|
|
|
- int id;
|
|
|
struct gpio_bank *bank;
|
|
|
+ int ret = 0;
|
|
|
|
|
|
- if (!pdev->dev.platform_data)
|
|
|
- return -EINVAL;
|
|
|
-
|
|
|
- pdata = pdev->dev.platform_data;
|
|
|
-
|
|
|
- if (!gpio_init_done) {
|
|
|
- int ret;
|
|
|
-
|
|
|
- ret = init_gpio_info(pdev);
|
|
|
- if (ret)
|
|
|
- return ret;
|
|
|
+ if (!pdev->dev.platform_data) {
|
|
|
+ ret = -EINVAL;
|
|
|
+ goto err_exit;
|
|
|
}
|
|
|
|
|
|
- id = pdev->id;
|
|
|
- bank = &gpio_bank[id];
|
|
|
+ bank = kzalloc(sizeof(struct gpio_bank), GFP_KERNEL);
|
|
|
+ if (!bank) {
|
|
|
+ dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto err_exit;
|
|
|
+ }
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
if (unlikely(!res)) {
|
|
|
- dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
|
|
|
- return -ENODEV;
|
|
|
+ dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n",
|
|
|
+ pdev->id);
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto err_free;
|
|
|
}
|
|
|
|
|
|
bank->irq = res->start;
|
|
|
+ bank->id = pdev->id;
|
|
|
+
|
|
|
+ pdata = pdev->dev.platform_data;
|
|
|
bank->virtual_irq_start = pdata->virtual_irq_start;
|
|
|
- bank->method = pdata->bank_type;
|
|
|
bank->dev = &pdev->dev;
|
|
|
bank->dbck_flag = pdata->dbck_flag;
|
|
|
bank->stride = pdata->bank_stride;
|
|
|
bank->width = pdata->bank_width;
|
|
|
-
|
|
|
+ bank->is_mpuio = pdata->is_mpuio;
|
|
|
+ bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
|
|
|
+ bank->loses_context = pdata->loses_context;
|
|
|
+ bank->get_context_loss_count = pdata->get_context_loss_count;
|
|
|
bank->regs = pdata->regs;
|
|
|
|
|
|
if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
|
|
@@ -1202,369 +1098,310 @@ static int __devinit omap_gpio_probe(struct platform_device *pdev)
|
|
|
/* Static mapping, never released */
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
if (unlikely(!res)) {
|
|
|
- dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
|
|
|
- return -ENODEV;
|
|
|
+ dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n",
|
|
|
+ pdev->id);
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto err_free;
|
|
|
}
|
|
|
|
|
|
bank->base = ioremap(res->start, resource_size(res));
|
|
|
if (!bank->base) {
|
|
|
- dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
|
|
|
- return -ENOMEM;
|
|
|
+ dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n",
|
|
|
+ pdev->id);
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto err_free;
|
|
|
}
|
|
|
|
|
|
+ platform_set_drvdata(pdev, bank);
|
|
|
+
|
|
|
pm_runtime_enable(bank->dev);
|
|
|
+ pm_runtime_irq_safe(bank->dev);
|
|
|
pm_runtime_get_sync(bank->dev);
|
|
|
|
|
|
- omap_gpio_mod_init(bank, id);
|
|
|
+ if (bank->is_mpuio)
|
|
|
+ mpuio_init(bank);
|
|
|
+
|
|
|
+ omap_gpio_mod_init(bank);
|
|
|
omap_gpio_chip_init(bank);
|
|
|
omap_gpio_show_rev(bank);
|
|
|
|
|
|
- if (!gpio_init_done)
|
|
|
- gpio_init_done = 1;
|
|
|
+ pm_runtime_put(bank->dev);
|
|
|
|
|
|
- return 0;
|
|
|
+ list_add_tail(&bank->node, &omap_gpio_list);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+
|
|
|
+err_free:
|
|
|
+ kfree(bank);
|
|
|
+err_exit:
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
|
|
-static int omap_gpio_suspend(void)
|
|
|
+#ifdef CONFIG_ARCH_OMAP2PLUS
|
|
|
+
|
|
|
+#if defined(CONFIG_PM_SLEEP)
|
|
|
+static int omap_gpio_suspend(struct device *dev)
|
|
|
{
|
|
|
- int i;
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
+ void __iomem *base = bank->base;
|
|
|
+ void __iomem *wakeup_enable;
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
- if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
|
|
+ if (!bank->mod_usage || !bank->loses_context)
|
|
|
return 0;
|
|
|
|
|
|
- for (i = 0; i < gpio_bank_count; i++) {
|
|
|
- struct gpio_bank *bank = &gpio_bank[i];
|
|
|
- void __iomem *wake_status;
|
|
|
- void __iomem *wake_clear;
|
|
|
- void __iomem *wake_set;
|
|
|
- unsigned long flags;
|
|
|
-
|
|
|
- switch (bank->method) {
|
|
|
-#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
- case METHOD_GPIO_1610:
|
|
|
- wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
|
|
|
- wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
- wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
|
- break;
|
|
|
-#endif
|
|
|
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
|
- case METHOD_GPIO_24XX:
|
|
|
- wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
|
|
|
- wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
- wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
|
|
- break;
|
|
|
-#endif
|
|
|
-#ifdef CONFIG_ARCH_OMAP4
|
|
|
- case METHOD_GPIO_44XX:
|
|
|
- wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
- wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
- wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
- break;
|
|
|
-#endif
|
|
|
- default:
|
|
|
- continue;
|
|
|
- }
|
|
|
+ if (!bank->regs->wkup_en || !bank->suspend_wakeup)
|
|
|
+ return 0;
|
|
|
|
|
|
- spin_lock_irqsave(&bank->lock, flags);
|
|
|
- bank->saved_wakeup = __raw_readl(wake_status);
|
|
|
- __raw_writel(0xffffffff, wake_clear);
|
|
|
- __raw_writel(bank->suspend_wakeup, wake_set);
|
|
|
- spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
- }
|
|
|
+ wakeup_enable = bank->base + bank->regs->wkup_en;
|
|
|
+
|
|
|
+ spin_lock_irqsave(&bank->lock, flags);
|
|
|
+ bank->saved_wakeup = __raw_readl(wakeup_enable);
|
|
|
+ _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
|
|
|
+ _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
|
|
|
+ spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static void omap_gpio_resume(void)
|
|
|
+static int omap_gpio_resume(struct device *dev)
|
|
|
{
|
|
|
- int i;
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
+ void __iomem *base = bank->base;
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
- if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
|
|
- return;
|
|
|
+ if (!bank->mod_usage || !bank->loses_context)
|
|
|
+ return 0;
|
|
|
|
|
|
- for (i = 0; i < gpio_bank_count; i++) {
|
|
|
- struct gpio_bank *bank = &gpio_bank[i];
|
|
|
- void __iomem *wake_clear;
|
|
|
- void __iomem *wake_set;
|
|
|
- unsigned long flags;
|
|
|
-
|
|
|
- switch (bank->method) {
|
|
|
-#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
- case METHOD_GPIO_1610:
|
|
|
- wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
- wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
|
- break;
|
|
|
-#endif
|
|
|
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
|
- case METHOD_GPIO_24XX:
|
|
|
- wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
- wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
|
|
- break;
|
|
|
-#endif
|
|
|
-#ifdef CONFIG_ARCH_OMAP4
|
|
|
- case METHOD_GPIO_44XX:
|
|
|
- wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
- wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
- break;
|
|
|
-#endif
|
|
|
- default:
|
|
|
- continue;
|
|
|
- }
|
|
|
+ if (!bank->regs->wkup_en || !bank->saved_wakeup)
|
|
|
+ return 0;
|
|
|
|
|
|
- spin_lock_irqsave(&bank->lock, flags);
|
|
|
- __raw_writel(0xffffffff, wake_clear);
|
|
|
- __raw_writel(bank->saved_wakeup, wake_set);
|
|
|
- spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
- }
|
|
|
-}
|
|
|
+ spin_lock_irqsave(&bank->lock, flags);
|
|
|
+ _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
|
|
|
+ _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
|
|
|
+ spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
-static struct syscore_ops omap_gpio_syscore_ops = {
|
|
|
- .suspend = omap_gpio_suspend,
|
|
|
- .resume = omap_gpio_resume,
|
|
|
-};
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#endif /* CONFIG_PM_SLEEP */
|
|
|
|
|
|
-#endif
|
|
|
+#if defined(CONFIG_PM_RUNTIME)
|
|
|
+static void omap_gpio_restore_context(struct gpio_bank *bank);
|
|
|
|
|
|
-#ifdef CONFIG_ARCH_OMAP2PLUS
|
|
|
+static int omap_gpio_runtime_suspend(struct device *dev)
|
|
|
+{
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
+ u32 l1 = 0, l2 = 0;
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
-static int workaround_enabled;
|
|
|
+ spin_lock_irqsave(&bank->lock, flags);
|
|
|
+ if (bank->power_mode != OFF_MODE) {
|
|
|
+ bank->power_mode = 0;
|
|
|
+ goto update_gpio_context_count;
|
|
|
+ }
|
|
|
+ /*
|
|
|
+ * If going to OFF, remove triggering for all
|
|
|
+ * non-wakeup GPIOs. Otherwise spurious IRQs will be
|
|
|
+ * generated. See OMAP2420 Errata item 1.101.
|
|
|
+ */
|
|
|
+ if (!(bank->enabled_non_wakeup_gpios))
|
|
|
+ goto update_gpio_context_count;
|
|
|
|
|
|
-void omap2_gpio_prepare_for_idle(int off_mode)
|
|
|
-{
|
|
|
- int i, c = 0;
|
|
|
- int min = 0;
|
|
|
+ bank->saved_datain = __raw_readl(bank->base +
|
|
|
+ bank->regs->datain);
|
|
|
+ l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
|
|
|
+ l2 = __raw_readl(bank->base + bank->regs->risingdetect);
|
|
|
|
|
|
- if (cpu_is_omap34xx())
|
|
|
- min = 1;
|
|
|
+ bank->saved_fallingdetect = l1;
|
|
|
+ bank->saved_risingdetect = l2;
|
|
|
+ l1 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
+ l2 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
|
|
|
- for (i = min; i < gpio_bank_count; i++) {
|
|
|
- struct gpio_bank *bank = &gpio_bank[i];
|
|
|
- u32 l1 = 0, l2 = 0;
|
|
|
- int j;
|
|
|
+ __raw_writel(l1, bank->base + bank->regs->fallingdetect);
|
|
|
+ __raw_writel(l2, bank->base + bank->regs->risingdetect);
|
|
|
|
|
|
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
|
|
- clk_disable(bank->dbck);
|
|
|
+ bank->workaround_enabled = true;
|
|
|
|
|
|
- if (!off_mode)
|
|
|
- continue;
|
|
|
+update_gpio_context_count:
|
|
|
+ if (bank->get_context_loss_count)
|
|
|
+ bank->context_loss_count =
|
|
|
+ bank->get_context_loss_count(bank->dev);
|
|
|
|
|
|
- /* If going to OFF, remove triggering for all
|
|
|
- * non-wakeup GPIOs. Otherwise spurious IRQs will be
|
|
|
- * generated. See OMAP2420 Errata item 1.101. */
|
|
|
- if (!(bank->enabled_non_wakeup_gpios))
|
|
|
- continue;
|
|
|
+ _gpio_dbck_disable(bank);
|
|
|
+ spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
- bank->saved_datain = __raw_readl(bank->base +
|
|
|
- OMAP24XX_GPIO_DATAIN);
|
|
|
- l1 = __raw_readl(bank->base +
|
|
|
- OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
- l2 = __raw_readl(bank->base +
|
|
|
- OMAP24XX_GPIO_RISINGDETECT);
|
|
|
- }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
|
|
|
- if (cpu_is_omap44xx()) {
|
|
|
- bank->saved_datain = __raw_readl(bank->base +
|
|
|
- OMAP4_GPIO_DATAIN);
|
|
|
- l1 = __raw_readl(bank->base +
|
|
|
- OMAP4_GPIO_FALLINGDETECT);
|
|
|
- l2 = __raw_readl(bank->base +
|
|
|
- OMAP4_GPIO_RISINGDETECT);
|
|
|
- }
|
|
|
+static int omap_gpio_runtime_resume(struct device *dev)
|
|
|
+{
|
|
|
+ struct platform_device *pdev = to_platform_device(dev);
|
|
|
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
+ int context_lost_cnt_after;
|
|
|
+ u32 l = 0, gen, gen0, gen1;
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
- bank->saved_fallingdetect = l1;
|
|
|
- bank->saved_risingdetect = l2;
|
|
|
- l1 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
- l2 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
+ spin_lock_irqsave(&bank->lock, flags);
|
|
|
+ _gpio_dbck_enable(bank);
|
|
|
+ if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) {
|
|
|
+ spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
|
|
|
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
- __raw_writel(l1, bank->base +
|
|
|
- OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
- __raw_writel(l2, bank->base +
|
|
|
- OMAP24XX_GPIO_RISINGDETECT);
|
|
|
+ if (bank->get_context_loss_count) {
|
|
|
+ context_lost_cnt_after =
|
|
|
+ bank->get_context_loss_count(bank->dev);
|
|
|
+ if (context_lost_cnt_after != bank->context_loss_count ||
|
|
|
+ !context_lost_cnt_after) {
|
|
|
+ omap_gpio_restore_context(bank);
|
|
|
+ } else {
|
|
|
+ spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
+ return 0;
|
|
|
}
|
|
|
+ }
|
|
|
|
|
|
- if (cpu_is_omap44xx()) {
|
|
|
- __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
|
|
|
- __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
|
|
|
- }
|
|
|
+ __raw_writel(bank->saved_fallingdetect,
|
|
|
+ bank->base + bank->regs->fallingdetect);
|
|
|
+ __raw_writel(bank->saved_risingdetect,
|
|
|
+ bank->base + bank->regs->risingdetect);
|
|
|
+ l = __raw_readl(bank->base + bank->regs->datain);
|
|
|
|
|
|
- c++;
|
|
|
- }
|
|
|
- if (!c) {
|
|
|
- workaround_enabled = 0;
|
|
|
- return;
|
|
|
- }
|
|
|
- workaround_enabled = 1;
|
|
|
-}
|
|
|
+ /*
|
|
|
+ * Check if any of the non-wakeup interrupt GPIOs have changed
|
|
|
+ * state. If so, generate an IRQ by software. This is
|
|
|
+ * horribly racy, but it's the best we can do to work around
|
|
|
+ * this silicon bug.
|
|
|
+ */
|
|
|
+ l ^= bank->saved_datain;
|
|
|
+ l &= bank->enabled_non_wakeup_gpios;
|
|
|
|
|
|
-void omap2_gpio_resume_after_idle(void)
|
|
|
-{
|
|
|
- int i;
|
|
|
- int min = 0;
|
|
|
+ /*
|
|
|
+ * No need to generate IRQs for the rising edge for gpio IRQs
|
|
|
+ * configured with falling edge only; and vice versa.
|
|
|
+ */
|
|
|
+ gen0 = l & bank->saved_fallingdetect;
|
|
|
+ gen0 &= bank->saved_datain;
|
|
|
|
|
|
- if (cpu_is_omap34xx())
|
|
|
- min = 1;
|
|
|
- for (i = min; i < gpio_bank_count; i++) {
|
|
|
- struct gpio_bank *bank = &gpio_bank[i];
|
|
|
- u32 l = 0, gen, gen0, gen1;
|
|
|
- int j;
|
|
|
+ gen1 = l & bank->saved_risingdetect;
|
|
|
+ gen1 &= ~(bank->saved_datain);
|
|
|
|
|
|
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
|
|
- clk_enable(bank->dbck);
|
|
|
+ /* FIXME: Consider GPIO IRQs with level detections properly! */
|
|
|
+ gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
|
|
|
+ /* Consider all GPIO IRQs needed to be updated */
|
|
|
+ gen |= gen0 | gen1;
|
|
|
|
|
|
- if (!workaround_enabled)
|
|
|
- continue;
|
|
|
+ if (gen) {
|
|
|
+ u32 old0, old1;
|
|
|
|
|
|
- if (!(bank->enabled_non_wakeup_gpios))
|
|
|
- continue;
|
|
|
+ old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
|
|
|
+ old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
- __raw_writel(bank->saved_fallingdetect,
|
|
|
- bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
- __raw_writel(bank->saved_risingdetect,
|
|
|
- bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
- l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
|
|
|
+ __raw_writel(old0 | gen, bank->base +
|
|
|
+ bank->regs->leveldetect0);
|
|
|
+ __raw_writel(old1 | gen, bank->base +
|
|
|
+ bank->regs->leveldetect1);
|
|
|
}
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
- __raw_writel(bank->saved_fallingdetect,
|
|
|
- bank->base + OMAP4_GPIO_FALLINGDETECT);
|
|
|
- __raw_writel(bank->saved_risingdetect,
|
|
|
- bank->base + OMAP4_GPIO_RISINGDETECT);
|
|
|
- l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
|
|
|
- }
|
|
|
-
|
|
|
- /* Check if any of the non-wakeup interrupt GPIOs have changed
|
|
|
- * state. If so, generate an IRQ by software. This is
|
|
|
- * horribly racy, but it's the best we can do to work around
|
|
|
- * this silicon bug. */
|
|
|
- l ^= bank->saved_datain;
|
|
|
- l &= bank->enabled_non_wakeup_gpios;
|
|
|
-
|
|
|
- /*
|
|
|
- * No need to generate IRQs for the rising edge for gpio IRQs
|
|
|
- * configured with falling edge only; and vice versa.
|
|
|
- */
|
|
|
- gen0 = l & bank->saved_fallingdetect;
|
|
|
- gen0 &= bank->saved_datain;
|
|
|
-
|
|
|
- gen1 = l & bank->saved_risingdetect;
|
|
|
- gen1 &= ~(bank->saved_datain);
|
|
|
-
|
|
|
- /* FIXME: Consider GPIO IRQs with level detections properly! */
|
|
|
- gen = l & (~(bank->saved_fallingdetect) &
|
|
|
- ~(bank->saved_risingdetect));
|
|
|
- /* Consider all GPIO IRQs needed to be updated */
|
|
|
- gen |= gen0 | gen1;
|
|
|
-
|
|
|
- if (gen) {
|
|
|
- u32 old0, old1;
|
|
|
-
|
|
|
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
- old0 = __raw_readl(bank->base +
|
|
|
- OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
- old1 = __raw_readl(bank->base +
|
|
|
- OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
- __raw_writel(old0 | gen, bank->base +
|
|
|
- OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
- __raw_writel(old1 | gen, bank->base +
|
|
|
- OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
- __raw_writel(old0, bank->base +
|
|
|
- OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
- __raw_writel(old1, bank->base +
|
|
|
- OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
- }
|
|
|
-
|
|
|
- if (cpu_is_omap44xx()) {
|
|
|
- old0 = __raw_readl(bank->base +
|
|
|
- OMAP4_GPIO_LEVELDETECT0);
|
|
|
- old1 = __raw_readl(bank->base +
|
|
|
- OMAP4_GPIO_LEVELDETECT1);
|
|
|
- __raw_writel(old0 | l, bank->base +
|
|
|
- OMAP4_GPIO_LEVELDETECT0);
|
|
|
- __raw_writel(old1 | l, bank->base +
|
|
|
- OMAP4_GPIO_LEVELDETECT1);
|
|
|
- __raw_writel(old0, bank->base +
|
|
|
- OMAP4_GPIO_LEVELDETECT0);
|
|
|
- __raw_writel(old1, bank->base +
|
|
|
- OMAP4_GPIO_LEVELDETECT1);
|
|
|
- }
|
|
|
+ __raw_writel(old0 | l, bank->base +
|
|
|
+ bank->regs->leveldetect0);
|
|
|
+ __raw_writel(old1 | l, bank->base +
|
|
|
+ bank->regs->leveldetect1);
|
|
|
}
|
|
|
+ __raw_writel(old0, bank->base + bank->regs->leveldetect0);
|
|
|
+ __raw_writel(old1, bank->base + bank->regs->leveldetect1);
|
|
|
}
|
|
|
|
|
|
+ bank->workaround_enabled = false;
|
|
|
+ spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
+
|
|
|
+ return 0;
|
|
|
}
|
|
|
+#endif /* CONFIG_PM_RUNTIME */
|
|
|
|
|
|
-#endif
|
|
|
+void omap2_gpio_prepare_for_idle(int pwr_mode)
|
|
|
+{
|
|
|
+ struct gpio_bank *bank;
|
|
|
+
|
|
|
+ list_for_each_entry(bank, &omap_gpio_list, node) {
|
|
|
+ if (!bank->mod_usage || !bank->loses_context)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ bank->power_mode = pwr_mode;
|
|
|
+
|
|
|
+ pm_runtime_put_sync_suspend(bank->dev);
|
|
|
+ }
|
|
|
+}
|
|
|
|
|
|
-#ifdef CONFIG_ARCH_OMAP3
|
|
|
-/* save the registers of bank 2-6 */
|
|
|
-void omap_gpio_save_context(void)
|
|
|
+void omap2_gpio_resume_after_idle(void)
|
|
|
{
|
|
|
- int i;
|
|
|
-
|
|
|
- /* saving banks from 2-6 only since GPIO1 is in WKUP */
|
|
|
- for (i = 1; i < gpio_bank_count; i++) {
|
|
|
- struct gpio_bank *bank = &gpio_bank[i];
|
|
|
- gpio_context[i].irqenable1 =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
|
- gpio_context[i].irqenable2 =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
|
- gpio_context[i].wake_en =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
|
- gpio_context[i].ctrl =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
- gpio_context[i].oe =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_OE);
|
|
|
- gpio_context[i].leveldetect0 =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
- gpio_context[i].leveldetect1 =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
- gpio_context[i].risingdetect =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
- gpio_context[i].fallingdetect =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
- gpio_context[i].dataout =
|
|
|
- __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
|
+ struct gpio_bank *bank;
|
|
|
+
|
|
|
+ list_for_each_entry(bank, &omap_gpio_list, node) {
|
|
|
+ if (!bank->mod_usage || !bank->loses_context)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ pm_runtime_get_sync(bank->dev);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
-/* restore the required registers of bank 2-6 */
|
|
|
-void omap_gpio_restore_context(void)
|
|
|
+#if defined(CONFIG_PM_RUNTIME)
|
|
|
+static void omap_gpio_restore_context(struct gpio_bank *bank)
|
|
|
{
|
|
|
- int i;
|
|
|
-
|
|
|
- for (i = 1; i < gpio_bank_count; i++) {
|
|
|
- struct gpio_bank *bank = &gpio_bank[i];
|
|
|
- __raw_writel(gpio_context[i].irqenable1,
|
|
|
- bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
|
- __raw_writel(gpio_context[i].irqenable2,
|
|
|
- bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
|
- __raw_writel(gpio_context[i].wake_en,
|
|
|
- bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
|
- __raw_writel(gpio_context[i].ctrl,
|
|
|
- bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
- __raw_writel(gpio_context[i].oe,
|
|
|
- bank->base + OMAP24XX_GPIO_OE);
|
|
|
- __raw_writel(gpio_context[i].leveldetect0,
|
|
|
- bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
- __raw_writel(gpio_context[i].leveldetect1,
|
|
|
- bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
- __raw_writel(gpio_context[i].risingdetect,
|
|
|
- bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
- __raw_writel(gpio_context[i].fallingdetect,
|
|
|
- bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
- __raw_writel(gpio_context[i].dataout,
|
|
|
- bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
|
+ __raw_writel(bank->context.wake_en,
|
|
|
+ bank->base + bank->regs->wkup_en);
|
|
|
+ __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
|
|
|
+ __raw_writel(bank->context.leveldetect0,
|
|
|
+ bank->base + bank->regs->leveldetect0);
|
|
|
+ __raw_writel(bank->context.leveldetect1,
|
|
|
+ bank->base + bank->regs->leveldetect1);
|
|
|
+ __raw_writel(bank->context.risingdetect,
|
|
|
+ bank->base + bank->regs->risingdetect);
|
|
|
+ __raw_writel(bank->context.fallingdetect,
|
|
|
+ bank->base + bank->regs->fallingdetect);
|
|
|
+ if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
|
|
+ __raw_writel(bank->context.dataout,
|
|
|
+ bank->base + bank->regs->set_dataout);
|
|
|
+ else
|
|
|
+ __raw_writel(bank->context.dataout,
|
|
|
+ bank->base + bank->regs->dataout);
|
|
|
+ __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
|
|
|
+
|
|
|
+ if (bank->dbck_enable_mask) {
|
|
|
+ __raw_writel(bank->context.debounce, bank->base +
|
|
|
+ bank->regs->debounce);
|
|
|
+ __raw_writel(bank->context.debounce_en,
|
|
|
+ bank->base + bank->regs->debounce_en);
|
|
|
}
|
|
|
+
|
|
|
+ __raw_writel(bank->context.irqenable1,
|
|
|
+ bank->base + bank->regs->irqenable);
|
|
|
+ __raw_writel(bank->context.irqenable2,
|
|
|
+ bank->base + bank->regs->irqenable2);
|
|
|
}
|
|
|
+#endif /* CONFIG_PM_RUNTIME */
|
|
|
+#else
|
|
|
+#define omap_gpio_suspend NULL
|
|
|
+#define omap_gpio_resume NULL
|
|
|
+#define omap_gpio_runtime_suspend NULL
|
|
|
+#define omap_gpio_runtime_resume NULL
|
|
|
#endif
|
|
|
|
|
|
+static const struct dev_pm_ops gpio_pm_ops = {
|
|
|
+ SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
|
|
|
+ SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
|
|
|
+ NULL)
|
|
|
+};
|
|
|
+
|
|
|
static struct platform_driver omap_gpio_driver = {
|
|
|
.probe = omap_gpio_probe,
|
|
|
.driver = {
|
|
|
.name = "omap_gpio",
|
|
|
+ .pm = &gpio_pm_ops,
|
|
|
},
|
|
|
};
|
|
|
|
|
|
@@ -1578,17 +1415,3 @@ static int __init omap_gpio_drv_reg(void)
|
|
|
return platform_driver_register(&omap_gpio_driver);
|
|
|
}
|
|
|
postcore_initcall(omap_gpio_drv_reg);
|
|
|
-
|
|
|
-static int __init omap_gpio_sysinit(void)
|
|
|
-{
|
|
|
- mpuio_init();
|
|
|
-
|
|
|
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
|
|
- if (cpu_is_omap16xx() || cpu_class_is_omap2())
|
|
|
- register_syscore_ops(&omap_gpio_syscore_ops);
|
|
|
-#endif
|
|
|
-
|
|
|
- return 0;
|
|
|
-}
|
|
|
-
|
|
|
-arch_initcall(omap_gpio_sysinit);
|
Arnd Bergmann