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@@ -32,6 +32,7 @@
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#define smnCPM_CONTROL 0x11180460
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_CNTL2 0x11180070
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+#define smnPCIE_CONFIG_CNTL 0x11180044
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u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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{
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{
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@@ -256,3 +257,15 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
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}
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}
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}
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}
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+
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+void nbio_v6_1_init_registers(struct amdgpu_device *adev)
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+{
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+ uint32_t def, data;
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+
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+ def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
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+ data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
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+ data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
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+
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+ if (def != data)
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+ WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
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+}
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