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@@ -84,6 +84,17 @@ static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
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{0, 0x1}
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};
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+/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
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+static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
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+ {6, 0x7},
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+ {5, 0x6},
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+ {4, 0x5},
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+ {3, 0x4},
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+ {2, 0x2},
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+ {1, 0x1},
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+ {0, 0x0}
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+};
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+
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/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
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static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
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{3, 0x3},
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@@ -577,6 +588,23 @@ static int brcmf_sdio_chip_recognition(struct brcmf_sdio_dev *sdiodev,
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ci->ramsize = 0xc0000;
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ci->rambase = 0x180000;
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break;
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+ case BCM43362_CHIP_ID:
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+ ci->c_inf[0].wrapbase = 0x18100000;
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+ ci->c_inf[0].cib = 0x27004211;
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+ ci->c_inf[1].id = BCMA_CORE_SDIO_DEV;
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+ ci->c_inf[1].base = 0x18002000;
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+ ci->c_inf[1].wrapbase = 0x18102000;
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+ ci->c_inf[1].cib = 0x0a004211;
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+ ci->c_inf[2].id = BCMA_CORE_INTERNAL_MEM;
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+ ci->c_inf[2].base = 0x18004000;
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+ ci->c_inf[2].wrapbase = 0x18104000;
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+ ci->c_inf[2].cib = 0x08080401;
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+ ci->c_inf[3].id = BCMA_CORE_ARM_CM3;
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+ ci->c_inf[3].base = 0x18003000;
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+ ci->c_inf[3].wrapbase = 0x18103000;
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+ ci->c_inf[3].cib = 0x03004211;
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+ ci->ramsize = 0x3C000;
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+ break;
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default:
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brcmf_err("chipid 0x%x is not supported\n", ci->chip);
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return -ENODEV;
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@@ -782,6 +810,11 @@ brcmf_sdio_chip_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
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brcmf_sdio_chip_name(ci->chip, chn, 8),
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drivestrength);
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break;
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+ case SDIOD_DRVSTR_KEY(BCM43362_CHIP_ID, 13):
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+ str_tab = sdiod_drive_strength_tab5_1v8;
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+ str_mask = 0x00003800;
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+ str_shift = 11;
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+ break;
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default:
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brcmf_err("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
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brcmf_sdio_chip_name(ci->chip, chn, 8),
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