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@@ -571,18 +571,14 @@ static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc)
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return val;
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}
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-static void armada_drm_primary_set(struct drm_crtc *crtc,
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- struct drm_plane *plane, int x, int y)
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+static void armada_drm_gra_plane_regs(struct armada_regs *regs,
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+ struct drm_framebuffer *fb, struct armada_plane_state *state,
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+ int x, int y, bool interlaced)
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{
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- struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
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- struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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- struct armada_regs regs[8];
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- bool interlaced = dcrtc->interlaced;
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- unsigned i;
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+ unsigned int i;
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u32 ctrl0;
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- i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced);
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-
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+ i = armada_drm_crtc_calc_fb(fb, x, y, regs, interlaced);
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armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN);
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armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN);
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armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN);
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@@ -598,6 +594,17 @@ static void armada_drm_primary_set(struct drm_crtc *crtc,
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CFG_GRA_HSMOOTH | CFG_GRA_ENA,
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LCD_SPU_DMA_CTRL0);
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armada_reg_queue_end(regs, i);
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+}
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+
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+static void armada_drm_primary_set(struct drm_crtc *crtc,
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+ struct drm_plane *plane, int x, int y)
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+{
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+ struct armada_plane_state *state = &drm_to_armada_plane(plane)->state;
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+ struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
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+ struct armada_regs regs[8];
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+ bool interlaced = dcrtc->interlaced;
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+
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+ armada_drm_gra_plane_regs(regs, plane->fb, state, x, y, interlaced);
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armada_drm_crtc_update_regs(dcrtc, regs);
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}
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