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@@ -1,15 +1,17 @@
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/*
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/*
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- * (c) 2005, 2006 Advanced Micro Devices, Inc.
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+ * (c) 2005-2012 Advanced Micro Devices, Inc.
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* Your use of this code is subject to the terms and conditions of the
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* Your use of this code is subject to the terms and conditions of the
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* GNU general public license version 2. See "COPYING" or
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* GNU general public license version 2. See "COPYING" or
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* http://www.gnu.org/licenses/gpl.html
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* http://www.gnu.org/licenses/gpl.html
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*
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*
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* Written by Jacob Shin - AMD, Inc.
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* Written by Jacob Shin - AMD, Inc.
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*
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*
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- * Support : jacob.shin@amd.com
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+ * Support: borislav.petkov@amd.com
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*
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*
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* April 2006
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* April 2006
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* - added support for AMD Family 0x10 processors
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* - added support for AMD Family 0x10 processors
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+ * May 2012
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+ * - major scrubbing
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*
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*
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* All MC4_MISCi registers are shared between multi-cores
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* All MC4_MISCi registers are shared between multi-cores
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*/
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*/
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