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@@ -4138,6 +4138,15 @@ static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
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}
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+static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
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+ uint32_t reg0, uint32_t reg1,
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+ uint32_t ref, uint32_t mask)
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+{
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+ int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
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+
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+ gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, ref, mask, 0x20);
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+}
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+
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static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
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enum amdgpu_interrupt_state state)
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{
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@@ -4459,6 +4468,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
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.emit_tmz = gfx_v9_0_ring_emit_tmz,
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.emit_wreg = gfx_v9_0_ring_emit_wreg,
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.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
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+ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
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};
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static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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@@ -4493,6 +4503,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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.set_priority = gfx_v9_0_ring_set_priority_compute,
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.emit_wreg = gfx_v9_0_ring_emit_wreg,
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.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
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+ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
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};
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static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
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@@ -4523,6 +4534,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
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.emit_rreg = gfx_v9_0_ring_emit_rreg,
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.emit_wreg = gfx_v9_0_ring_emit_wreg,
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.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
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+ .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
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};
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static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
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