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@@ -4553,6 +4553,30 @@ static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
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return 0;
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}
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+static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev)
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+{
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+ int pos;
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+ u32 cap, ctrl;
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+
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+ if (!pci_quirk_intel_spt_pch_acs_match(dev))
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+ return -ENOTTY;
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+
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+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
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+ if (!pos)
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+ return -ENOTTY;
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+
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+ pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
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+ pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
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+
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+ ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
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+
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+ pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
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+
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+ pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
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+
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+ return 0;
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+}
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+
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static const struct pci_dev_acs_ops {
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u16 vendor;
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u16 device;
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@@ -4564,6 +4588,7 @@ static const struct pci_dev_acs_ops {
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},
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
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.enable_acs = pci_quirk_enable_intel_spt_pch_acs,
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+ .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir,
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},
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};
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