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@@ -4,12 +4,16 @@ The IP core used inside these SoCs has 3 banks of 32 GPIOs each.
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The registers of all the banks are interwoven inside one single IO range.
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The registers of all the banks are interwoven inside one single IO range.
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We load one GPIO controller instance per bank. To make this possible
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We load one GPIO controller instance per bank. To make this possible
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we support 2 types of nodes. The parent node defines the memory I/O range and
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we support 2 types of nodes. The parent node defines the memory I/O range and
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-has 3 children each describing a single bank.
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+has 3 children each describing a single bank. Also the GPIO controller can receive
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+interrupts on any of the GPIOs, either edge or level. It then interrupts the CPU
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+using GIC INT12.
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Required properties for the top level node:
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Required properties for the top level node:
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- compatible:
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- compatible:
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- "mediatek,mt7621-gpio" for Mediatek controllers
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- "mediatek,mt7621-gpio" for Mediatek controllers
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- reg : Physical base address and length of the controller's registers
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- reg : Physical base address and length of the controller's registers
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+- interrupt-parent : phandle of the parent interrupt controller.
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+- interrupts = Interrupt specifier for the controllers interrupt
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Required properties for the GPIO bank node:
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Required properties for the GPIO bank node:
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- compatible:
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- compatible:
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@@ -28,6 +32,9 @@ Example:
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compatible = "mediatek,mt7621-gpio";
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compatible = "mediatek,mt7621-gpio";
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reg = <0x600 0x100>;
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reg = <0x600 0x100>;
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+ interrupt-parent = <&gic>;
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+ interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
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+
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gpio0: bank@0 {
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gpio0: bank@0 {
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reg = <0>;
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reg = <0>;
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compatible = "mediatek,mt7621-gpio-bank";
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compatible = "mediatek,mt7621-gpio-bank";
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