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@@ -210,10 +210,10 @@ static int iwl_rx_init(struct iwl_priv *priv)
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iwl_trans_rx_hw_init(priv, rxq);
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- spin_lock_irqsave(&priv->lock, flags);
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+ spin_lock_irqsave(&priv->shrd->lock, flags);
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rxq->need_update = 1;
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iwl_rx_queue_update_write_ptr(priv, rxq);
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- spin_unlock_irqrestore(&priv->lock, flags);
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+ spin_unlock_irqrestore(&priv->shrd->lock, flags);
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return 0;
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}
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@@ -546,7 +546,7 @@ static int iwl_tx_init(struct iwl_priv *priv)
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alloc = true;
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}
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- spin_lock_irqsave(&priv->lock, flags);
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+ spin_lock_irqsave(&priv->shrd->lock, flags);
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/* Turn off all Tx DMA fifos */
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iwl_write_prph(priv, SCD_TXFACT, 0);
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@@ -554,7 +554,7 @@ static int iwl_tx_init(struct iwl_priv *priv)
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/* Tell NIC where to find the "keep warm" buffer */
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iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
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- spin_unlock_irqrestore(&priv->lock, flags);
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+ spin_unlock_irqrestore(&priv->shrd->lock, flags);
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/* Alloc and init all Tx queues, including the command queue (#4/#9) */
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for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
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@@ -598,13 +598,13 @@ static int iwl_nic_init(struct iwl_priv *priv)
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unsigned long flags;
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/* nic_init */
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- spin_lock_irqsave(&priv->lock, flags);
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+ spin_lock_irqsave(&priv->shrd->lock, flags);
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iwl_apm_init(priv);
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/* Set interrupt coalescing calibration timer to default (512 usecs) */
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iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
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- spin_unlock_irqrestore(&priv->lock, flags);
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+ spin_unlock_irqrestore(&priv->shrd->lock, flags);
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iwl_set_pwr_vmain(priv);
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@@ -728,7 +728,7 @@ static int iwl_trans_start_device(struct iwl_priv *priv)
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/*
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* Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
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- * must be called under priv->lock and mac access
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+ * must be called under priv->shrd->lock and mac access
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*/
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static void iwl_trans_txq_set_sched(struct iwl_priv *priv, u32 mask)
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{
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@@ -777,7 +777,7 @@ static void iwl_trans_tx_start(struct iwl_priv *priv)
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int i, chan;
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u32 reg_val;
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- spin_lock_irqsave(&priv->lock, flags);
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+ spin_lock_irqsave(&priv->shrd->lock, flags);
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priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
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a = priv->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
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@@ -872,7 +872,7 @@ static void iwl_trans_tx_start(struct iwl_priv *priv)
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iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
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}
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- spin_unlock_irqrestore(&priv->lock, flags);
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+ spin_unlock_irqrestore(&priv->shrd->lock, flags);
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/* Enable L1-Active */
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iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
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@@ -888,7 +888,7 @@ static int iwl_trans_tx_stop(struct iwl_priv *priv)
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unsigned long flags;
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/* Turn off all Tx DMA fifos */
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- spin_lock_irqsave(&priv->lock, flags);
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+ spin_lock_irqsave(&priv->shrd->lock, flags);
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iwl_trans_txq_set_sched(priv, 0);
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@@ -902,7 +902,7 @@ static int iwl_trans_tx_stop(struct iwl_priv *priv)
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" DMA channel %d [0x%08x]", ch,
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iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
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}
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- spin_unlock_irqrestore(&priv->lock, flags);
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+ spin_unlock_irqrestore(&priv->shrd->lock, flags);
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if (!priv->txq) {
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IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
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@@ -924,9 +924,9 @@ static void iwl_trans_stop_device(struct iwl_priv *priv)
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iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
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/* tell the device to stop sending interrupts */
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- spin_lock_irqsave(&priv->lock, flags);
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+ spin_lock_irqsave(&priv->shrd->lock, flags);
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iwl_disable_interrupts(priv);
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- spin_unlock_irqrestore(&priv->lock, flags);
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+ spin_unlock_irqrestore(&priv->shrd->lock, flags);
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trans_sync_irq(&priv->trans);
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/* device going down, Stop using ICT table */
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