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@@ -113,7 +113,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
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(ctx->mv_count * ctx->mv_size);
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break;
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case S5P_MFC_CODEC_MPEG4_DEC:
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- if (IS_MFCV7(dev)) {
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+ if (IS_MFCV7_PLUS(dev)) {
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ctx->scratch_buf_size =
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S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
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mb_width,
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@@ -354,7 +354,7 @@ static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
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ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
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/* MFCv7 needs pad bytes for Luma and Chroma */
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- if (IS_MFCV7(ctx->dev)) {
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+ if (IS_MFCV7_PLUS(ctx->dev)) {
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ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
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ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
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}
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@@ -1303,7 +1303,7 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
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WRITEL(ctx->display_delay, mfc_regs->d_display_delay);
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}
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- if (IS_MFCV7(dev)) {
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+ if (IS_MFCV7_PLUS(dev)) {
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WRITEL(reg, mfc_regs->d_dec_options);
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reg = 0;
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}
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@@ -1318,7 +1318,7 @@ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
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if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
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reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
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- if (IS_MFCV7(dev))
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+ if (IS_MFCV7_PLUS(dev))
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WRITEL(reg, mfc_regs->d_init_buffer_options);
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else
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WRITEL(reg, mfc_regs->d_dec_options);
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@@ -1406,7 +1406,7 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
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}
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/* Set stride lengths for v7 & above */
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- if (IS_MFCV7(dev)) {
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+ if (IS_MFCV7_PLUS(dev)) {
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WRITEL(ctx->img_width, mfc_regs->e_source_first_plane_stride);
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WRITEL(ctx->img_width, mfc_regs->e_source_second_plane_stride);
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}
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@@ -2148,7 +2148,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
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R(e_h264_frame_packing_sei_info,
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S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
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- if (!IS_MFCV7(dev))
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+ if (!IS_MFCV7_PLUS(dev))
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goto done;
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/* Initialize registers used in MFC v7 */
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