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@@ -102,34 +102,34 @@ struct exynos_pcie {
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#define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7)
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#define PCIE_PHY_TRSV3_LVCC 0x31c
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-static void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
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+static void exynos_elb_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
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{
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- writel(val, pcie->elbi_base + reg);
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+ writel(val, exynos_pcie->elbi_base + reg);
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}
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-static u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg)
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+static u32 exynos_elb_readl(struct exynos_pcie *exynos_pcie, u32 reg)
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{
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- return readl(pcie->elbi_base + reg);
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+ return readl(exynos_pcie->elbi_base + reg);
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}
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-static void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
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+static void exynos_phy_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
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{
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- writel(val, pcie->phy_base + reg);
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+ writel(val, exynos_pcie->phy_base + reg);
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}
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-static u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg)
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+static u32 exynos_phy_readl(struct exynos_pcie *exynos_pcie, u32 reg)
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{
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- return readl(pcie->phy_base + reg);
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+ return readl(exynos_pcie->phy_base + reg);
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}
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-static void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg)
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+static void exynos_blk_writel(struct exynos_pcie *exynos_pcie, u32 val, u32 reg)
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{
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- writel(val, pcie->block_base + reg);
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+ writel(val, exynos_pcie->block_base + reg);
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}
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-static u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg)
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+static u32 exynos_blk_readl(struct exynos_pcie *exynos_pcie, u32 reg)
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{
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- return readl(pcie->block_base + reg);
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+ return readl(exynos_pcie->block_base + reg);
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}
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static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on)
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