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@@ -34,6 +34,9 @@
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#include <asm/kvm_coproc.h>
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#include <asm/kvm_mmu.h>
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+/* Maximum phys_shift supported for any VM on this host */
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+static u32 kvm_ipa_limit;
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+
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/*
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* ARMv8 Reset Values
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*/
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@@ -135,6 +138,46 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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return kvm_timer_vcpu_reset(vcpu);
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}
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+void kvm_set_ipa_limit(void)
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+{
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+ unsigned int ipa_max, pa_max, va_max, parange;
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+
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+ parange = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1) & 0x7;
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+ pa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
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+
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+ /* Clamp the IPA limit to the PA size supported by the kernel */
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+ ipa_max = (pa_max > PHYS_MASK_SHIFT) ? PHYS_MASK_SHIFT : pa_max;
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+ /*
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+ * Since our stage2 table is dependent on the stage1 page table code,
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+ * we must always honor the following condition:
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+ *
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+ * Number of levels in Stage1 >= Number of levels in Stage2.
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+ *
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+ * So clamp the ipa limit further down to limit the number of levels.
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+ * Since we can concatenate upto 16 tables at entry level, we could
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+ * go upto 4bits above the maximum VA addressible with the current
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+ * number of levels.
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+ */
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+ va_max = PGDIR_SHIFT + PAGE_SHIFT - 3;
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+ va_max += 4;
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+
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+ if (va_max < ipa_max)
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+ ipa_max = va_max;
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+
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+ /*
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+ * If the final limit is lower than the real physical address
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+ * limit of the CPUs, report the reason.
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+ */
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+ if (ipa_max < pa_max)
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+ pr_info("kvm: Limiting the IPA size due to kernel %s Address limit\n",
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+ (va_max < pa_max) ? "Virtual" : "Physical");
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+
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+ WARN(ipa_max < KVM_PHYS_SHIFT,
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+ "KVM IPA limit (%d bit) is smaller than default size\n", ipa_max);
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+ kvm_ipa_limit = ipa_max;
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+ kvm_info("IPA Size Limit: %dbits\n", kvm_ipa_limit);
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+}
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+
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/*
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* Configure the VTCR_EL2 for this VM. The VTCR value is common
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* across all the physical CPUs on the system. We use system wide
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