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@@ -1460,19 +1460,19 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
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struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL;
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- if (table_info == NULL)
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- return -EINVAL;
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-
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- sclk_table = table_info->vdd_dep_on_sclk;
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-
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for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) {
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vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
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if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) {
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- if (0 == phm_get_sclk_for_voltage_evv(hwmgr,
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+ if ((hwmgr->pp_table_version == PP_TABLE_V1)
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+ && !phm_get_sclk_for_voltage_evv(hwmgr,
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table_info->vddgfx_lookup_table, vv_id, &sclk)) {
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_ClockStretcher)) {
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+ if (table_info == NULL)
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+ return -EINVAL;
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+ sclk_table = table_info->vdd_dep_on_sclk;
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+
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for (j = 1; j < sclk_table->count; j++) {
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if (sclk_table->entries[j].clk == sclk &&
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sclk_table->entries[j].cks_enable == 0) {
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@@ -1498,12 +1498,15 @@ static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr)
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}
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}
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} else {
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-
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if ((hwmgr->pp_table_version == PP_TABLE_V0)
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|| !phm_get_sclk_for_voltage_evv(hwmgr,
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table_info->vddc_lookup_table, vv_id, &sclk)) {
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_ClockStretcher)) {
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+ if (table_info == NULL)
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+ return -EINVAL;
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+ sclk_table = table_info->vdd_dep_on_sclk;
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+
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for (j = 1; j < sclk_table->count; j++) {
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if (sclk_table->entries[j].clk == sclk &&
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sclk_table->entries[j].cks_enable == 0) {
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