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@@ -94,7 +94,6 @@ void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
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write_nic_dword(dev, dwRegAddr, NewValue);
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} else
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write_nic_dword(dev, dwRegAddr, dwData);
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- return;
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}
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u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
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@@ -215,7 +214,6 @@ static void rtl8192_phy_RFSerialWrite(struct net_device *dev,
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}
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rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
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}
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- return;
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}
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void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
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@@ -256,7 +254,6 @@ void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
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} else
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rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
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}
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- return;
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}
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u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
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@@ -399,7 +396,6 @@ void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
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Rtl819XAGCTAB_Array_Table[i+1]);
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}
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}
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- return;
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}
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static void rtl8192_InitBBRFRegDef(struct net_device *dev)
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@@ -640,7 +636,6 @@ void rtl8192_phy_getTxPower(struct net_device *dev)
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RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
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rOFDM0_RxDetector3, priv->framesync);
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priv->SifsTime = read_nic_word(dev, SIFS);
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- return;
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}
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void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
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@@ -694,7 +689,6 @@ void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
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__func__);
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break;
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}
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- return;
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}
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bool rtl8192_phy_RFConfig(struct net_device *dev)
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@@ -723,7 +717,6 @@ bool rtl8192_phy_RFConfig(struct net_device *dev)
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void rtl8192_phy_updateInitGain(struct net_device *dev)
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{
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- return;
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}
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u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
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@@ -813,7 +806,6 @@ static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
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"unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
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break;
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}
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- return;
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}
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static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable,
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