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@@ -81,13 +81,6 @@ static inline void gic_write(unsigned int reg, unsigned long val)
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return gic_write64(reg, (u64)val);
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return gic_write64(reg, (u64)val);
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}
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}
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-static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
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-{
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- gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
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- GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
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- GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
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-}
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-
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static bool gic_local_irq_is_routable(int intr)
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static bool gic_local_irq_is_routable(int intr)
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{
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{
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u32 vpe_ctl;
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u32 vpe_ctl;
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@@ -294,7 +287,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
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spin_lock_irqsave(&gic_lock, flags);
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spin_lock_irqsave(&gic_lock, flags);
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/* Re-route this IRQ */
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/* Re-route this IRQ */
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- gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
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+ write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpumask_first(&tmp))));
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/* Update the pcpu_masks */
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/* Update the pcpu_masks */
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for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
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for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
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@@ -486,7 +479,7 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
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spin_lock_irqsave(&gic_lock, flags);
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spin_lock_irqsave(&gic_lock, flags);
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write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
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write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
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- gic_map_to_vpe(intr, mips_cm_vp_id(vpe));
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+ write_gic_map_vp(intr, BIT(mips_cm_vp_id(vpe)));
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for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
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for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
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clear_bit(intr, pcpu_masks[i].pcpu_mask);
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clear_bit(intr, pcpu_masks[i].pcpu_mask);
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set_bit(intr, pcpu_masks[vpe].pcpu_mask);
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set_bit(intr, pcpu_masks[vpe].pcpu_mask);
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