|
@@ -802,7 +802,7 @@ static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
|
|
|
|
|
|
static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
|
|
|
{
|
|
|
- unsigned long ssp_clk = drv_data->max_clk_rate;
|
|
|
+ unsigned long ssp_clk = drv_data->master->max_speed_hz;
|
|
|
const struct ssp_device *ssp = drv_data->ssp;
|
|
|
|
|
|
rate = min_t(int, ssp_clk, rate);
|
|
@@ -1217,13 +1217,13 @@ static int setup(struct spi_device *spi)
|
|
|
/* NOTE: PXA25x_SSP _could_ use external clocking ... */
|
|
|
cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, spi->bits_per_word);
|
|
|
if (!pxa25x_ssp_comp(drv_data))
|
|
|
- dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
|
|
|
- drv_data->max_clk_rate
|
|
|
+ dev_dbg(&spi->dev, "%u Hz actual, %s\n",
|
|
|
+ drv_data->master->max_speed_hz
|
|
|
/ (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
|
|
|
chip->enable_dma ? "DMA" : "PIO");
|
|
|
else
|
|
|
- dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
|
|
|
- drv_data->max_clk_rate / 2
|
|
|
+ dev_dbg(&spi->dev, "%u Hz actual, %s\n",
|
|
|
+ drv_data->master->max_speed_hz / 2
|
|
|
/ (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
|
|
|
chip->enable_dma ? "DMA" : "PIO");
|
|
|
|
|
@@ -1473,7 +1473,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|
|
/* Enable SOC clock */
|
|
|
clk_prepare_enable(ssp->clk);
|
|
|
|
|
|
- drv_data->max_clk_rate = clk_get_rate(ssp->clk);
|
|
|
+ master->max_speed_hz = clk_get_rate(ssp->clk);
|
|
|
|
|
|
/* Load default SSP configuration */
|
|
|
pxa2xx_spi_write(drv_data, SSCR0, 0);
|