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@@ -1,34 +1,29 @@
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-/*
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- * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
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- *
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- * Author: Timur Tabi <timur@freescale.com>
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- *
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- * Copyright 2007-2010 Freescale Semiconductor, Inc.
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- *
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- * This file is licensed under the terms of the GNU General Public License
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- * version 2. This program is licensed "as is" without any warranty of any
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- * kind, whether express or implied.
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- *
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- *
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- * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
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- *
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- * The i.MX SSI core has some nasty limitations in AC97 mode. While most
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- * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
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- * one FIFO which combines all valid receive slots. We cannot even select
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- * which slots we want to receive. The WM9712 with which this driver
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- * was developed with always sends GPIO status data in slot 12 which
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- * we receive in our (PCM-) data stream. The only chance we have is to
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- * manually skip this data in the FIQ handler. With sampling rates different
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- * from 48000Hz not every frame has valid receive data, so the ratio
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- * between pcm data and GPIO status data changes. Our FIQ handler is not
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- * able to handle this, hence this driver only works with 48000Hz sampling
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- * rate.
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- * Reading and writing AC97 registers is another challenge. The core
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- * provides us status bits when the read register is updated with *another*
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- * value. When we read the same register two times (and the register still
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- * contains the same value) these status bits are not set. We work
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- * around this by not polling these bits but only wait a fixed delay.
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- */
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+// SPDX-License-Identifier: GPL-2.0
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+//
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+// Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
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+//
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+// Author: Timur Tabi <timur@freescale.com>
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+//
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+// Copyright 2007-2010 Freescale Semiconductor, Inc.
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+//
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+// Some notes why imx-pcm-fiq is used instead of DMA on some boards:
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+//
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+// The i.MX SSI core has some nasty limitations in AC97 mode. While most
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+// sane processor vendors have a FIFO per AC97 slot, the i.MX has only
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+// one FIFO which combines all valid receive slots. We cannot even select
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+// which slots we want to receive. The WM9712 with which this driver
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+// was developed with always sends GPIO status data in slot 12 which
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+// we receive in our (PCM-) data stream. The only chance we have is to
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+// manually skip this data in the FIQ handler. With sampling rates different
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+// from 48000Hz not every frame has valid receive data, so the ratio
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+// between pcm data and GPIO status data changes. Our FIQ handler is not
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+// able to handle this, hence this driver only works with 48000Hz sampling
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+// rate.
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+// Reading and writing AC97 registers is another challenge. The core
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+// provides us status bits when the read register is updated with *another*
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+// value. When we read the same register two times (and the register still
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+// contains the same value) these status bits are not set. We work
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+// around this by not polling these bits but only wait a fixed delay.
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#include <linux/init.h>
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#include <linux/io.h>
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