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@@ -5,7 +5,10 @@
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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+#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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interrupt-parent = <&intc>;
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@@ -13,6 +16,41 @@
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#address-cells = <2>;
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#size-cells = <2>;
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+ aliases {
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+ i2c0 = &i2c0;
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+ i2c1 = &i2c1;
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+ i2c2 = &i2c2;
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+ i2c3 = &i2c3;
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+ i2c4 = &i2c4;
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+ i2c5 = &i2c5;
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+ i2c6 = &i2c6;
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+ i2c7 = &i2c7;
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+ i2c8 = &i2c8;
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+ i2c9 = &i2c9;
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+ i2c10 = &i2c10;
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+ i2c11 = &i2c11;
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+ i2c12 = &i2c12;
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+ i2c13 = &i2c13;
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+ i2c14 = &i2c14;
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+ i2c15 = &i2c15;
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+ spi0 = &spi0;
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+ spi1 = &spi1;
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+ spi2 = &spi2;
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+ spi3 = &spi3;
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+ spi4 = &spi4;
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+ spi5 = &spi5;
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+ spi6 = &spi6;
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+ spi7 = &spi7;
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+ spi8 = &spi8;
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+ spi9 = &spi9;
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+ spi10 = &spi10;
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+ spi11 = &spi11;
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+ spi12 = &spi12;
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+ spi13 = &spi13;
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+ spi14 = &spi14;
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+ spi15 = &spi15;
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+ };
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+
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chosen { };
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memory@80000000 {
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@@ -152,6 +190,11 @@
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};
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};
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+ pmu {
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+ compatible = "arm,armv8-pmuv3";
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+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
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@@ -206,6 +249,457 @@
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#power-domain-cells = <1>;
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};
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+ qupv3_id_0: geniqup@8c0000 {
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+ compatible = "qcom,geni-se-qup";
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+ reg = <0x8c0000 0x6000>;
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+ clock-names = "m-ahb", "s-ahb";
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+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ i2c0: i2c@880000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x880000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c0_default>;
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+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi0: spi@880000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x880000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi0_default>;
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+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c1: i2c@884000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x884000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c1_default>;
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+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi1: spi@884000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x884000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi1_default>;
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+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c2: i2c@888000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x888000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c2_default>;
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+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi2: spi@888000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x888000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi2_default>;
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+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c3: i2c@88c000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x88c000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c3_default>;
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+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi3: spi@88c000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x88c000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi3_default>;
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+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c4: i2c@890000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x890000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c4_default>;
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+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi4: spi@890000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x890000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi4_default>;
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+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c5: i2c@894000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x894000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c5_default>;
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+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi5: spi@894000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x894000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi5_default>;
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+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c6: i2c@898000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x898000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c6_default>;
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+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi6: spi@898000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x898000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi6_default>;
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+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c7: i2c@89c000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0x89c000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c7_default>;
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+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi7: spi@89c000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0x89c000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi7_default>;
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+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ qupv3_id_1: geniqup@ac0000 {
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+ compatible = "qcom,geni-se-qup";
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+ reg = <0xac0000 0x6000>;
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+ clock-names = "m-ahb", "s-ahb";
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+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
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+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges;
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+ status = "disabled";
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+
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+ i2c8: i2c@a80000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0xa80000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c8_default>;
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+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi8: spi@a80000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0xa80000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi8_default>;
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+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c9: i2c@a84000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0xa84000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c9_default>;
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+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi9: spi@a84000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0xa84000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_spi9_default>;
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+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ uart9: serial@a84000 {
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+ compatible = "qcom,geni-debug-uart";
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+ reg = <0xa84000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_uart9_default>;
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+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ i2c10: i2c@a88000 {
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+ compatible = "qcom,geni-i2c";
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+ reg = <0xa88000 0x4000>;
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+ clock-names = "se";
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+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&qup_i2c10_default>;
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+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ spi10: spi@a88000 {
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+ compatible = "qcom,geni-spi";
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+ reg = <0xa88000 0x4000>;
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|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_spi10_default>;
|
|
|
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c11: i2c@a8c000 {
|
|
|
+ compatible = "qcom,geni-i2c";
|
|
|
+ reg = <0xa8c000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_i2c11_default>;
|
|
|
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi11: spi@a8c000 {
|
|
|
+ compatible = "qcom,geni-spi";
|
|
|
+ reg = <0xa8c000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_spi11_default>;
|
|
|
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c12: i2c@a90000 {
|
|
|
+ compatible = "qcom,geni-i2c";
|
|
|
+ reg = <0xa90000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_i2c12_default>;
|
|
|
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi12: spi@a90000 {
|
|
|
+ compatible = "qcom,geni-spi";
|
|
|
+ reg = <0xa90000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_spi12_default>;
|
|
|
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c13: i2c@a94000 {
|
|
|
+ compatible = "qcom,geni-i2c";
|
|
|
+ reg = <0xa94000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_i2c13_default>;
|
|
|
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi13: spi@a94000 {
|
|
|
+ compatible = "qcom,geni-spi";
|
|
|
+ reg = <0xa94000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_spi13_default>;
|
|
|
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c14: i2c@a98000 {
|
|
|
+ compatible = "qcom,geni-i2c";
|
|
|
+ reg = <0xa98000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_i2c14_default>;
|
|
|
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi14: spi@a98000 {
|
|
|
+ compatible = "qcom,geni-spi";
|
|
|
+ reg = <0xa98000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_spi14_default>;
|
|
|
+ interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ i2c15: i2c@a9c000 {
|
|
|
+ compatible = "qcom,geni-i2c";
|
|
|
+ reg = <0xa9c000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_i2c15_default>;
|
|
|
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+
|
|
|
+ spi15: spi@a9c000 {
|
|
|
+ compatible = "qcom,geni-spi";
|
|
|
+ reg = <0xa9c000 0x4000>;
|
|
|
+ clock-names = "se";
|
|
|
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
|
|
|
+ pinctrl-names = "default";
|
|
|
+ pinctrl-0 = <&qup_spi15_default>;
|
|
|
+ interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ status = "disabled";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
tcsr_mutex_regs: syscon@1f40000 {
|
|
|
compatible = "syscon";
|
|
|
reg = <0x1f40000 0x40000>;
|
|
|
@@ -219,6 +713,253 @@
|
|
|
#gpio-cells = <2>;
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <2>;
|
|
|
+
|
|
|
+ qup_i2c0_default: qup-i2c0-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio0", "gpio1";
|
|
|
+ function = "qup0";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c1_default: qup-i2c1-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio17", "gpio18";
|
|
|
+ function = "qup1";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c2_default: qup-i2c2-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio27", "gpio28";
|
|
|
+ function = "qup2";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c3_default: qup-i2c3-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio41", "gpio42";
|
|
|
+ function = "qup3";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c4_default: qup-i2c4-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio89", "gpio90";
|
|
|
+ function = "qup4";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c5_default: qup-i2c5-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio85", "gpio86";
|
|
|
+ function = "qup5";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c6_default: qup-i2c6-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio45", "gpio46";
|
|
|
+ function = "qup6";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c7_default: qup-i2c7-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio93", "gpio94";
|
|
|
+ function = "qup7";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c8_default: qup-i2c8-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio65", "gpio66";
|
|
|
+ function = "qup8";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c9_default: qup-i2c9-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio6", "gpio7";
|
|
|
+ function = "qup9";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c10_default: qup-i2c10-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio55", "gpio56";
|
|
|
+ function = "qup10";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c11_default: qup-i2c11-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio31", "gpio32";
|
|
|
+ function = "qup11";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c12_default: qup-i2c12-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio49", "gpio50";
|
|
|
+ function = "qup12";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c13_default: qup-i2c13-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio105", "gpio106";
|
|
|
+ function = "qup13";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c14_default: qup-i2c14-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio33", "gpio34";
|
|
|
+ function = "qup14";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_i2c15_default: qup-i2c15-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio81", "gpio82";
|
|
|
+ function = "qup15";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi0_default: qup-spi0-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio0", "gpio1",
|
|
|
+ "gpio2", "gpio3";
|
|
|
+ function = "qup0";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi1_default: qup-spi1-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio17", "gpio18",
|
|
|
+ "gpio19", "gpio20";
|
|
|
+ function = "qup1";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi2_default: qup-spi2-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio27", "gpio28",
|
|
|
+ "gpio29", "gpio30";
|
|
|
+ function = "qup2";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi3_default: qup-spi3-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio41", "gpio42",
|
|
|
+ "gpio43", "gpio44";
|
|
|
+ function = "qup3";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi4_default: qup-spi4-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio89", "gpio90",
|
|
|
+ "gpio91", "gpio92";
|
|
|
+ function = "qup4";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi5_default: qup-spi5-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio85", "gpio86",
|
|
|
+ "gpio87", "gpio88";
|
|
|
+ function = "qup5";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi6_default: qup-spi6-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio45", "gpio46",
|
|
|
+ "gpio47", "gpio48";
|
|
|
+ function = "qup6";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi7_default: qup-spi7-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio93", "gpio94",
|
|
|
+ "gpio95", "gpio96";
|
|
|
+ function = "qup7";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi8_default: qup-spi8-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio65", "gpio66",
|
|
|
+ "gpio67", "gpio68";
|
|
|
+ function = "qup8";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi9_default: qup-spi9-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio6", "gpio7",
|
|
|
+ "gpio4", "gpio5";
|
|
|
+ function = "qup9";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi10_default: qup-spi10-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio55", "gpio56",
|
|
|
+ "gpio53", "gpio54";
|
|
|
+ function = "qup10";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi11_default: qup-spi11-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio31", "gpio32",
|
|
|
+ "gpio33", "gpio34";
|
|
|
+ function = "qup11";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi12_default: qup-spi12-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio49", "gpio50",
|
|
|
+ "gpio51", "gpio52";
|
|
|
+ function = "qup12";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi13_default: qup-spi13-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio105", "gpio106",
|
|
|
+ "gpio107", "gpio108";
|
|
|
+ function = "qup13";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi14_default: qup-spi14-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio33", "gpio34",
|
|
|
+ "gpio31", "gpio32";
|
|
|
+ function = "qup14";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_spi15_default: qup-spi15-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio81", "gpio82",
|
|
|
+ "gpio83", "gpio84";
|
|
|
+ function = "qup15";
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ qup_uart9_default: qup-uart9-default {
|
|
|
+ pinmux {
|
|
|
+ pins = "gpio4", "gpio5";
|
|
|
+ function = "qup9";
|
|
|
+ };
|
|
|
+ };
|
|
|
};
|
|
|
|
|
|
spmi_bus: spmi@c440000 {
|
|
|
@@ -246,6 +987,29 @@
|
|
|
#mbox-cells = <1>;
|
|
|
};
|
|
|
|
|
|
+ apps_rsc: rsc@179c0000 {
|
|
|
+ label = "apps_rsc";
|
|
|
+ compatible = "qcom,rpmh-rsc";
|
|
|
+ reg = <0x179c0000 0x10000>,
|
|
|
+ <0x179d0000 0x10000>,
|
|
|
+ <0x179e0000 0x10000>;
|
|
|
+ reg-names = "drv-0", "drv-1", "drv-2";
|
|
|
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ qcom,tcs-offset = <0xd00>;
|
|
|
+ qcom,drv-id = <2>;
|
|
|
+ qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
|
+ <SLEEP_TCS 3>,
|
|
|
+ <WAKE_TCS 3>,
|
|
|
+ <CONTROL_TCS 1>;
|
|
|
+
|
|
|
+ rpmhcc: clock-controller {
|
|
|
+ compatible = "qcom,sdm845-rpmh-clk";
|
|
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+ #clock-cells = <1>;
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+ };
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+ };
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+
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|
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intc: interrupt-controller@17a00000 {
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compatible = "arm,gic-v3";
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#address-cells = <1>;
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Andy Gross