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@@ -66,6 +66,70 @@ static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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/* Make sure we use phases which we can enumerate with */
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if (!IS_ERR(priv->sample_clk))
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clk_set_phase(priv->sample_clk, priv->default_sample_phase);
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+
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+ /*
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+ * Set the drive phase offset based on speed mode to achieve hold times.
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+ *
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+ * NOTE: this is _not_ a value that is dynamically tuned and is also
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+ * _not_ a value that will vary from board to board. It is a value
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+ * that could vary between different SoC models if they had massively
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+ * different output clock delays inside their dw_mmc IP block (delay_o),
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+ * but since it's OK to overshoot a little we don't need to do complex
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+ * calculations and can pick values that will just work for everyone.
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+ *
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+ * When picking values we'll stick with picking 0/90/180/270 since
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+ * those can be made very accurately on all known Rockchip SoCs.
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+ *
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+ * Note that these values match values from the DesignWare Databook
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+ * tables for the most part except for SDR12 and "ID mode". For those
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+ * two modes the databook calculations assume a clock in of 50MHz. As
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+ * seen above, we always use a clock in rate that is exactly the
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+ * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
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+ * back out before the controller sees it).
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+ *
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+ * From measurement of a single device, it appears that delay_o is
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+ * about .5 ns. Since we try to leave a bit of margin, it's expected
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+ * that numbers here will be fine even with much larger delay_o
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+ * (the 1.4 ns assumed by the DesignWare Databook would result in the
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+ * same results, for instance).
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+ */
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+ if (!IS_ERR(priv->drv_clk)) {
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+ int phase;
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+
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+ /*
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+ * In almost all cases a 90 degree phase offset will provide
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+ * sufficient hold times across all valid input clock rates
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+ * assuming delay_o is not absurd for a given SoC. We'll use
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+ * that as a default.
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+ */
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+ phase = 90;
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+
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+ switch (ios->timing) {
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+ case MMC_TIMING_MMC_DDR52:
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+ /*
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+ * Since clock in rate with MMC_DDR52 is doubled when
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+ * bus width is 8 we need to double the phase offset
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+ * to get the same timings.
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+ */
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+ if (ios->bus_width == MMC_BUS_WIDTH_8)
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+ phase = 180;
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+ break;
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+ case MMC_TIMING_UHS_SDR104:
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+ case MMC_TIMING_MMC_HS200:
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+ /*
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+ * In the case of 150 MHz clock (typical max for
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+ * Rockchip SoCs), 90 degree offset will add a delay
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+ * of 1.67 ns. That will meet min hold time of .8 ns
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+ * as long as clock output delay is < .87 ns. On
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+ * SoCs measured this seems to be OK, but it doesn't
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+ * hurt to give margin here, so we use 180.
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+ */
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+ phase = 180;
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+ break;
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+ }
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+
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+ clk_set_phase(priv->drv_clk, phase);
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+ }
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}
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#define NUM_PHASES 360
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@@ -233,10 +297,10 @@ static int dw_mci_rockchip_init(struct dw_mci *host)
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/* Common capabilities of RK3288 SoC */
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static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
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- MMC_CAP_ERASE,
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- MMC_CAP_ERASE,
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- MMC_CAP_ERASE,
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- MMC_CAP_ERASE,
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+ MMC_CAP_ERASE | MMC_CAP_CMD23,
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+ MMC_CAP_ERASE | MMC_CAP_CMD23,
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+ MMC_CAP_ERASE | MMC_CAP_CMD23,
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+ MMC_CAP_ERASE | MMC_CAP_CMD23,
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};
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static const struct dw_mci_drv_data rk2928_drv_data = {
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Linus Torvalds