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@@ -403,6 +403,7 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
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I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL1);
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}
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+ intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
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break;
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case PORT_CLK_SEL_WRPLL2:
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plls->wrpll2_refcount--;
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@@ -413,13 +414,12 @@ void intel_ddi_put_crtc_pll(struct drm_crtc *crtc)
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I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE);
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POSTING_READ(WRPLL_CTL2);
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}
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+ intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
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break;
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}
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WARN(plls->wrpll1_refcount < 0, "Invalid WRPLL1 refcount\n");
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WARN(plls->wrpll2_refcount < 0, "Invalid WRPLL2 refcount\n");
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-
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- intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_NONE;
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}
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#define LC_FREQ 2700
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@@ -739,7 +739,6 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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{
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struct drm_crtc *crtc = &intel_crtc->base;
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struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
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- struct drm_encoder *encoder = &intel_encoder->base;
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struct drm_i915_private *dev_priv = crtc->dev->dev_private;
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struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
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int type = intel_encoder->type;
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@@ -748,26 +747,7 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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intel_ddi_put_crtc_pll(crtc);
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- if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
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- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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-
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- switch (intel_dp->link_bw) {
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- case DP_LINK_BW_1_62:
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- intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
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- break;
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- case DP_LINK_BW_2_7:
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- intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
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- break;
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- case DP_LINK_BW_5_4:
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- intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
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- break;
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- default:
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- DRM_ERROR("Link bandwidth %d unsupported\n",
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- intel_dp->link_bw);
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- return false;
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- }
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-
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- } else if (type == INTEL_OUTPUT_HDMI) {
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+ if (type == INTEL_OUTPUT_HDMI) {
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uint32_t reg, val;
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unsigned p, n2, r2;
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@@ -808,14 +788,6 @@ bool intel_ddi_pll_select(struct intel_crtc *intel_crtc)
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plls->wrpll2_refcount++;
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intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
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}
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-
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- } else if (type == INTEL_OUTPUT_ANALOG) {
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- DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
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- pipe_name(pipe));
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- intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_SPLL;
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- } else {
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- WARN(1, "Invalid DDI encoder type %d\n", type);
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- return false;
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}
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return true;
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