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@@ -619,6 +619,102 @@ static void omap_8250_unthrottle(struct uart_port *port)
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}
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#ifdef CONFIG_SERIAL_8250_DMA
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+static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir);
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+
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+static void __dma_rx_do_complete(struct uart_8250_port *p, bool error)
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+{
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+ struct uart_8250_dma *dma = p->dma;
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+ struct tty_port *tty_port = &p->port.state->port;
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+ struct dma_tx_state state;
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+ int count;
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+
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+ dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
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+ dma->rx_size, DMA_FROM_DEVICE);
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+
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+ dma->rx_running = 0;
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+ dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
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+ dmaengine_terminate_all(dma->rxchan);
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+
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+ count = dma->rx_size - state.residue;
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+
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+ tty_insert_flip_string(tty_port, dma->rx_buf, count);
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+ p->port.icount.rx += count;
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+ if (!error)
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+ omap_8250_rx_dma(p, 0);
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+
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+ tty_flip_buffer_push(tty_port);
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+}
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+
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+static void __dma_rx_complete(void *param)
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+{
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+ __dma_rx_do_complete(param, false);
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+}
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+
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+static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
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+{
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+ struct uart_8250_dma *dma = p->dma;
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+ struct dma_async_tx_descriptor *desc;
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+
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+ switch (iir & 0x3f) {
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+ case UART_IIR_RLSI:
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+ /* 8250_core handles errors and break interrupts */
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+ if (dma->rx_running) {
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+ dmaengine_pause(dma->rxchan);
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+ __dma_rx_do_complete(p, true);
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+ }
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+ return -EIO;
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+ case UART_IIR_RX_TIMEOUT:
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+ /*
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+ * If RCVR FIFO trigger level was not reached, complete the
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+ * transfer and let 8250_core copy the remaining data.
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+ */
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+ if (dma->rx_running) {
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+ dmaengine_pause(dma->rxchan);
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+ __dma_rx_do_complete(p, true);
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+ }
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+ return -ETIMEDOUT;
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+ case UART_IIR_RDI:
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+ /*
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+ * The OMAP UART is a special BEAST. If we receive RDI we _have_
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+ * a DMA transfer programmed but it didn't work. One reason is
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+ * that we were too slow and there were too many bytes in the
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+ * FIFO, the UART counted wrong and never kicked the DMA engine
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+ * to do anything. That means once we receive RDI on OMAP then
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+ * the DMA won't do anything soon so we have to cancel the DMA
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+ * transfer and purge the FIFO manually.
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+ */
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+ if (dma->rx_running) {
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+ dmaengine_pause(dma->rxchan);
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+ __dma_rx_do_complete(p, true);
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+ }
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+ return -ETIMEDOUT;
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+
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+ default:
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+ break;
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+ }
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+
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+ if (dma->rx_running)
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+ return 0;
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+
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+ desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
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+ dma->rx_size, DMA_DEV_TO_MEM,
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+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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+ if (!desc)
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+ return -EBUSY;
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+
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+ dma->rx_running = 1;
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+ desc->callback = __dma_rx_complete;
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+ desc->callback_param = p;
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+
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+ dma->rx_cookie = dmaengine_submit(desc);
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+
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+ dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
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+ dma->rx_size, DMA_FROM_DEVICE);
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+
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+ dma_async_issue_pending(dma->rxchan);
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+ return 0;
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+}
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+
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static int omap_8250_tx_dma(struct uart_8250_port *p);
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static void omap_8250_dma_tx_complete(void *param)
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