|
@@ -8259,6 +8259,7 @@ restart_ih:
|
|
|
static int cik_startup(struct radeon_device *rdev)
|
|
|
{
|
|
|
struct radeon_ring *ring;
|
|
|
+ u32 nop;
|
|
|
int r;
|
|
|
|
|
|
/* enable pcie gen2/3 link */
|
|
@@ -8392,9 +8393,15 @@ static int cik_startup(struct radeon_device *rdev)
|
|
|
}
|
|
|
cik_irq_set(rdev);
|
|
|
|
|
|
+ if (rdev->family == CHIP_HAWAII) {
|
|
|
+ nop = RADEON_CP_PACKET2;
|
|
|
+ } else {
|
|
|
+ nop = PACKET3(PACKET3_NOP, 0x3FFF);
|
|
|
+ }
|
|
|
+
|
|
|
ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
|
|
|
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
|
|
|
- PACKET3(PACKET3_NOP, 0x3FFF));
|
|
|
+ nop);
|
|
|
if (r)
|
|
|
return r;
|
|
|
|
|
@@ -8402,7 +8409,7 @@ static int cik_startup(struct radeon_device *rdev)
|
|
|
/* type-2 packets are deprecated on MEC, use type-3 instead */
|
|
|
ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
|
|
|
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
|
|
|
- PACKET3(PACKET3_NOP, 0x3FFF));
|
|
|
+ nop);
|
|
|
if (r)
|
|
|
return r;
|
|
|
ring->me = 1; /* first MEC */
|
|
@@ -8413,7 +8420,7 @@ static int cik_startup(struct radeon_device *rdev)
|
|
|
/* type-2 packets are deprecated on MEC, use type-3 instead */
|
|
|
ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
|
|
|
r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
|
|
|
- PACKET3(PACKET3_NOP, 0x3FFF));
|
|
|
+ nop);
|
|
|
if (r)
|
|
|
return r;
|
|
|
/* dGPU only have 1 MEC */
|